PULSE-COUNTING (DIGITAL) SERVOS
The basic function of the electronic section of a videorecorder or disc-player servo system is to measure time (i.e. the period between arrival of reference and sample pulses) in the case of the phase control loop; and frequency (FG rate) for the speed control loop. Both these functions can be carried out with great speed and accuracy by means of digital counter/timer circuits using a crystal clock as a basic ‘metronome’.
An arrangement for a digitally based phase control servo is given in Fig. 15.3, in which the crystal clock on the left produces 1 μs- interval pulses. The input reference pulse is used to enable counter 1, which commences to count clock pulses from 0000000000 upwards. In this 10-bit counter the maximum count is 210, which corresponds to decimal 1024. At the clock rate of 1 MHz the counter will take about 1 ms to reach maximum count. Before this happens, however, a sample pulse appears and activates the latch, which effectively ‘freezes’ the count at that instant and transfers it to the hold register of a digital comparator. If the sample pulse comes 500 μs after the
reference pulse the count will have reached about 512 (binary 1000000000). The latch operates and binary 512 is loaded into the comparator as an indication of the time lapse between the arrival of the two pulses.
Now consider the upper section of Fig. 15.3. On emergence from the ÷2 stage the clock pulses are at 500 kHz, 2 μs intervals. They are fed to a second 10-bit counter (counter 2) which also counts from zero to 1024, resetting itself each time it fills up. The count-and-reset process for counter 2 is continuous, and because it is counting 500 kHz (2 μs period) pulses it resets at 1024 × 2 μs = 2 ms intervals. At each reset a trigger pulse is applied to the set input of an SR bist- able, whose output is thus set high. The continuous count made by counter 2 is also fed to the comparator which is designed to detect coincidence between the binary numbers in its ‘hold’ and ‘compare’ registers. After 1 ms, counter 2 will have reached 512 so that the counts in the two comparator registers match. Under these circumstances the comparator output goes high; this pulse is passed to the ‘R’ input of the SR bistable, resetting its output low. The bi- stable is being set and reset at 1 ms intervals to give an output whose mark/space ratio is 1:1.
Suppose the motor speeds up. The sample pulse will come early, giving counter 1 little time to accumulate a count before the latch operates. A correspondingly low number, say 256, is loaded into the hold register of the comparator. Counter 2, having set the SR bi- stable high when it passed zero, will take only 500 μs to accumulate a count of 256 to satisfy the comparator and reset the bistable low again. It will remain low for 1500 μs (1.5 ms) before being set high once more by counter 2 passing zero. The mark/space ratio of the bistable output signal is now 1:3. The opposite applies if the motor slows down for any reason. Whereas the rising edges of the bistable output waveform always occur at 2 ms intervals (see Fig. 15.3) due to the regular resetting action of counter 2, the timing of the falling edges is determined entirely by the time lapse between reference and sample pulses.
The pulse-width-modulated (PWM) squarewave output is
converted to a d.c. error voltage by passing it through an RC integrating filter. The output from this is used to modify motor speed.
Digital speed correction
The arrangement of Fig. 15.3 is fundamentally a measurer of time. In order to use it in a speed-control loop some modification is required, as shown in Fig. 15.4. Waveform a is the FG tone,
amplitude-limited to produce squarewave b. Its rising edge triggers a short monostable to produce pulse train c; its falling edge triggers a second monostable whose output is pulse train d. Each pulse ‘c’ enables counter 1 and each pulse ‘d’ resets the counter and operates the latch. The latch count is inversely proportional to FG frequency, and is held in the comparator’s hold register until counter 2 (whose configuration and function are the same as in Fig. 15.3) reaches the same count, whereupon the bistable is reset. The varying M/S ratio is processed as already described, and now produces an error voltage which reflects the frequency of the FG input signal. For this speed control application the bistable set/reset rate is required to be faster than the 1 kHz rate typical of a digital phase corrector, and an output rate between 4 and 17 kHz is general. In either case the bistable rate is determined by the clock rate and the number of bits (maximum possible count) of the recirculating counter – counter 2 in the present Figs 15.3 and 15.4. These are chosen to suit the sampling rate to the application loop in which it is used.
In some videorecorder designs the counter bit capacities and clock
rates vary with different loop requirements in drum and capstan servos. Advanced designs also incorporate a ROM in the digitial servo chip to provide different counting conditions for varying deck conditions, i.e. SP/LP operation and ‘trick-speed’ replay modes; the ROM is addressed by a mode select line whose origin is the user’s function keyboard.