BRIGHTNESS, CONTRAST AND COLOUR CONTROL
Provided that the black areas of the picture can be made to drive the picture-tube just to beam cut-off (and this can be achieved automatically, see later), and if viewing were always in low or zero ambient light, the only picture control necessary would be a contrast control, with a link to the colour (saturation) control line. Because viewing conditions vary greatly, as do viewers’ tastes, all three controls are generally provided, though often relegated to semi-accessible presets. For brightness control, the d.c. level on which the entire picture sits is raised and lowered, generally by altering the pedestal clamp reference voltage. For control of contrast the gain of the Y-signal amplifier must be varied while maintaining correct black-level; because any adjustment of contrast requires a proportional adjustment of colour level, the user contrast control will generally influence the chroma gain by means of an electrical ‘tracking link’ between the two. Colour level (user control) and colour/contrast tracking are carried out by varying the gain of the chrominance amplifier.
There are several internal influences on these analogue control lines. Excessive beam current in the picture-tube is detected by a sensing circuit which pulls down brightness, contrast or both to prevent excessive dissipation in the picture-tube’s shadowmask. Some sets have ambient light sensors to adjust contrast to suit the viewing conditions. As an internal loop in the decoder, an a.c.c. (automatic colour control) circuit monitors the amplitude of the burst signal and adjusts chroma gain accordingly; this maintains correct saturation level in the face of chroma signal amplitude variations due to propagation conditions, mistuning etc.
COLOUR DECODER
The low-level signal processing stages in a colour decoder are ideally suited to IC technology. An internal diagram of a typical chip is illustrated in Fig. 7.6.
The luminance signal is applied at pin 8, having passed through the delay line and subcarrier trap. The input coupling capacitor also serves as reservoir for the black-level clamping carried out within the chip. Luminance black-level is referred to an internally generated volt- age pulse. Thus conditioned, the Y signal passes on to the R, G and B primary-colour matrices.
The chroma-separating bandpass filter feeds 4.43 MHz chroma signal and burst to IC pin 4. The first function within the chip is a.c.c., whereby chroma signal amplitude is regulated according to
received burst level as seen by the peak detector – the control potential reservoir is the capacitor at IC pin 3. Regulated chroma signal now enters a voltage-controlled attenuator to come under the influence of the d.c. voltage coming in to pin 5 from the user control – this may be cabinet-mounted or part of a cordless remote control. The effect of the saturation control is removed once per TV line – for the duration of the burst signal. Thus the amplitude of the burst is unaffected by the setting of the colour control, and it travels, along with whatever level of chroma signal has been set, through the chrominance amplifier and buffer stages and out of the chip on pin 28 for application to the external glass delay line and matrix circuit. Separated and averaged U and V signals re-enter the chip on pins 22 and 23 respectively, for passage to the de-weighting circuits and synchronous demodulators. Once demodulated, the B−Y and R−Y signals take two paths – to the G−Y matrix and to the primary- colour matrices, where each colour-difference signal is recombined with the luminance signal to make R, G and B signals for onward progress towards the picture-tube.
Because the burst signal has a ±90° phase shift, it does not get ‘aver-aged’ in the delay line matrix. It is input to the phase-locked-loop for subcarrier regeneration and services the entire ‘reference’ circuitry in the lower left-hand section of the chip diagram. It first encounters the burst gate where signal chroma is eliminated.
The subcarrier oscillator in this circuit runs at twice subcarrier frequency, 8.867238 MHz. Its frequency is divided by two and 90° phase shifted on its way to a phase detector wherein it is compared with incoming burst: the RC network between pins 24 and 25 form a low-pass filter whose long time-constant keeps the PLL steady at mean burst phase. Thus is the loop completed, with the advantage that the 2 × fsc locked oscillator can render, via ÷2 circuits, correctly phased quadrature reference feeds to the two demodulators. En route to the V (R−Y) demodulator the reference feed is inverted on a line- by-line basis by the PAL switch, driven in turn by a bistable flip-flop circuit.
The flip-flop acts as a ÷2 stage on line-rate trigger pulses, but must be steered by an ident detector to ensure that the PAL switch phase is correct. Ident monitoring is carried out in the H/2 detector, which compares V signal polarity with V demodulator drive phase. When the two disagree a reset pulse is passed to the ident stage, thence to the flip-flop. The latter misses one beat, thus ‘phasing up’ to the incoming PAL signal. Once PAL ident has been corrected, the colour- killer block opens the synchronous demodulators permitting colour to reach the screen.
A second function of the H/2 detector is that of a.c.c. control element. Its output is proportional to burst amplitude and is turned into a control voltage by a peak detector for application to the controlled chroma amplifier. This loop maintains constant burst amplitude, hence correct saturation level in the picture.
The crystals and transistors at the bottom of the diagram indicate the dual-standard capabilities of this IC. A switching voltage introduced at pin 25 will put the chip into NTSC mode, with PAL switch disabled, time-constant removed from the PLL error voltage line, and 3.58 MHz or 4.43 MHz reference selected by turning on the appropriate crystal-switching transistor. The necessary tint control is switched in across pins 24 and 25.
From the Y matrices the RGB signals (only B shown in full detail in Fig. 7.6) each enter a data switch. At a command from pin 9 this changes stage, passing to the output stages locally generated RGB signals applied to pins 12, 14 and 16; they may typically come from an inbuilt teletext decoder or from a personal computer via a rear- mounted multipin plug/socket. These signals come under the influ- ence of the contrast and brightness control stages next downstream in each channel. According to the d.c. voltage presented on pins 6 and 11 of the chip, these adjust the gain and d.c. operating points of all three RGB channels in parallel. These stages are necessarily perfectly matched by virtue of their simultaneous fabrication on a single silicion substrate. The controlled signals now pass through a clamping amplifier, blanker and buffer stage before passing out of the chip on pins 13(R), 15(G) and 17(B) to the high-level tube drive amplifier stage described at the beginning of this chapter.
The penultimate clamping amplifier has the special function of automatically setting up the black-levels for each colour according to the gun cut-off characteristic of the picture tube in use. During the field blanking interval each gun of the tube in turn is driven just to cut-off point by a specially shaped and timed pulse from the IC. The measured cathode current is fed back into the IC on its pin 18 (black current information input); three pulses are received in quick succession, one for each gun, and are directed to the appropriate clamps in the IC. The measured currents are in each case converted to a clamp reference voltage, stored for R, G and B on the capacitors at pins 10, 20 and 19 respectively. By this means the three colours on the screen are made to cut off at exactly the same point on the reproduced grey-scale, regardless of ageing or manufacturing tolerances in the tube, and with no need for manual adjustment. The less commonly required (and less noticeable on viewing) need for drive adjustment to neutralise highlight tinting must still be provided – and made when gun emission or phosphor efficiency drops.
All control pulses for blanking, keying, clamping and gating enter the IC on pin 7. The waveform here is a ‘sandcastle’ shape, whose lower level contains line and field-rate blanking pulses, and whose upper level contains a short line-rate pulse coinciding with the period of the colour burst. It is sorted out by level detectors within the IC, and generated by the horizontal sync processing chip in the set’s time- base section.