microcontrollers

5.3 INTERFACING INPUT DEVICES

The interfacing of input devices is almost identical to that of interfacing output devices, but with some differences in bus signals and circuit components. In this discussion, we will assume that you are familiar with the basic concepts of inter­facing (Section 5.1.3) and describe only the additional details. First, we examine the execution and timing of the IN instruction and discuss the interfacing of input devices in relation to the timing diagram.

5.3.1 IN Instruction

The Z80 instruction set includes several instructions to read (copy) data from such. Input devices as switches, keyboards, and A/D data converters. These instruc­tions can read an input device and place the data into the accumulator, Z80 reg­isters, or memory registers. These are two-byte instructions; the first byte is the opcode, and the second byte specifies the port address. Although there are numerous ways of specifying the port address, it is always eight bits long. Thus, the addresses for input devices can range from 00_H to FF_H• among the several Input instructions available, the machine cycles and timing of the following instruction will be examined.

When the microprocessor is asked to execute these instructions, it will first read the machine codes (or bytes) stored at locations 2065_H and 2066_H, then read the switch positions at port 84_H by enabling the interfacing device of the port. The data byte indicating switch positions from the input port will be placed in the accumulator. To design an interfacing circuit with the port address 84_H• we now need to examine the machine cycles and execution timing of the IN instruction.

5.3.2 Execution of IN Instruction and Its Timing:

The IN instruction has three machine cycles: Opcode Fetch, Memory Read, and I/O Read. In the first two machine cycles, the Z80 reads the opcode DB and the port address 84_H (see example in previous section). These cycles are identical to the first two machine cycles of the OUT instruction shown in Figure 5.1. In the third machine cycle, the Z80 reads a data byte from the input port as follows (Figure 5.7):

1. The port address 84_H is placed on the low-order address bus at the beginning of the machine cycle M₃ (I/O Read).

2. During T₂, the control signals I͞͞O͞R͞Q͞ and R̅D̅ are asserted, and one Wait state is inserted automatically after T₂•

3. During T₃, the Z80 reads the data bus and then causes the control signals (I͞͞O͞R͞Q͞ and R̅D̅) to go inactive.

5.3.3 Basic Concepts in Interfacing Input Devices

To interface an input port with the address 84_H, we need to logically AND the information on the address bus with the control signals and enable the input port. The steps are as follows:

1. Decode the low-order bus to generate the I/O address pulse.

2. Combine the I/O address pulse with the control signals I͞͞O͞R͞Q͞ and R̅D̅ to gen­erate the signal I/O Select (I̅O̅S̅E̅L̅, Figure5.8). Another approach is to combine I͞͞O͞R͞Q͞ and R̅D̅ to generate an I̅O̅R̅D̅ signal and then to combine the I̅O̅R̅D̅ with the I/O address pulse to generate the I/O select pulse.

3. Enable the input interfacing device using the I/O select pulse.

These steps are identical to those listed for interfacing output devices; the only differences are (1) the control signal is R̅D̅ instead of W̅R̅, and (2) data flow from an input port to the accumulator rather than from the accumulator to an output port.

5.2 ILLUSTRATIVE EXAMPLE 1: INTERFACING LEDS

In this section, we will analyze an actual interfacing circuit with the port address 07_H to display binary data at an LED port and a single digit at a seven-segment LED. A group of 8 LEDs will be used to indicate binary I s and Os and will be’ connected to the data bus using the 7475 latches. Similarly, an interfacing of a seven-segment LED will be demonstrated using an octal latch 74LS373.

5.2.1 Hardware

Figure 5.3 shows the logic symbols of the 7475 latch. It has four bistable latches controlled by the active high enable signals; E₁_₂ enables the first two latches and E_3-4 enables the remaining two. When E is high, data enter the latch and appear at the Q outputs, and Q outputs correspond to the input data, When E goes from high to low, data will be latched and will remain stable until E goes high again.

. When Q output is high, it can supply (source) 400 µA, and when it is low, it can sink 16 mA current. Since most LEDs require a 10-15 mA current to be prop­erly illuminated, they are connected to ͞Q output of the latch so that when the input is high, ͞Q output is low and the LED is turned on.

Figure 5.3(b) shows the logic symbol of an octal latch 74LS373. This is sim­ilar to the 7475 latch, except that the latch is followed by a tri-state buffer. The latch and the buffer are controlled independently by Latch Enable (LE) and Out­put Enable (O͞E͞). When LE goes high, the data enter the latch, and when LE goes low, data are latched. The latched data are available on the output lines of the 74LS373 if the buffer is enabled by O͞E͞ (active low). If O͞E͞ is high, the output lines go into high impedance state. The advantage of using the octal latch is that it has eight latches in a package (vs. four in 7475), and when the buffer is not enabled, it remains in high impedance state, thus minimizing the loading on the data bus. In addition, it has two control signals (LE and O͞E͞); this can be advantageous in some interfacing circuits.

5.2.2 Interfacing Circuit

Figure 5.4 shows an interfacing circuit for the LED output port with the address 07 _H. We will analyze this circuit in terms of the three steps for interfacing output devices as outlined in Section 5.1.3.

1. An 8-input NAND gate with five inverters is used to decode the low-order address bus A₇-A₀. The output of the NAND gate is asserted when the address is 0 0 0 0 0 1 1 1 (07_H); thus, the NAND gate performs the decoding function to generate the I/O address (l͞O͞A͞D͞R͞) pulse.

2. The control signals I͞͞O͞R͞Q͞ and W͞͞R͞ are ANDed in a negative AND gate (physically, an OR gate) to generate the control signal IOW͞͞R͞ (active low). The IOW͞͞R͞ is again ANDed (through a NOR gate) with the I/O address pulse to

generate the I/O select pulse (active high).The IOSEL pulse is asserted only when the address is 07_H and the control signals I͞͞O͞R͞Q͞ and W͞͞R͞ are low.

3. The IOSEL pulse is used to enable the latches 7475. The data bus D₇-D₀ is connected to the D input, and the LED cathodes are connected to the Q̅ output of the latch. The LED anodes are connected to the + 5 V power supply through the current-limiting resistors.

At the beginning of T₂ in the third machine cycle shown in Figure 5.1, the control signals I͞O͞R͞Q͞ and ̅W̅͞͞R̅͞ are asserted, and the I/O select pulse (Figure 5.4) goes high If the address is 07_H• When the I/O select pulse goes high, the data on the data bus enter the latches. During T₃, when the control signals become inac­tive, the I/O select pulse goes low, and the data are latched. The logic is on the data lines turn on the corresponding LEDs because when a data bit is high, the Q̅ output is low and the LED is turned on.

INSTRUCTIONS

To display data, for example, 97_H, at this LED port, instructions are as follows:

The first instruction (LD) stores the second byte 97_H in the accumulator, and the OUT instruction sends the byte (97_H) from the accumulator to the LED port 07_H• When the l/O select pulse is asserted, the byte 97_H enters the latch and is displayed by the LEDs. When LOSEL goes low (inactive), the byte is latched and continues to be displayed by the LEDs.

5.2.3 Using a Seven-Segment LED as a Display Device

A seven-segment LED consists of seven light-emitting diodes (A through G) and one diode (DP) for the decimal point; these LEDs are physically arranged as shown in Figure 5.5(a). To display a number, the necessary segments are lit by sending an appropriate signal for current flow through diodes. For example, to display 8, all segments should be lit. To display I, segments Band C must be lit. Seven-segment LEOs are available in two types: common cathode and common anode. They can be represented schematically as in Figures 5.5(b) and (c). The segments, A through G, are usually connected to data lines D₀ through 0₆, re­spectively. If the decimal point is being used, data line D₇ is connected to DP; otherwise it can be left open. Current flow in these diodes must be limited to 20mA.

Figure 5.6 shows the interfacing of a common-anode seven-segment LED using the latch 74LS373. This circuit assumes the same decoding network as in Figure 5.4, thus assigning the port address 07_H to the latch. The differences be­tween Figures 5.4 and 5.6 are that the binary LEDs in Figure 5.4 are replaced by the seven-segment LED, and the latch 7475 is replaced by the octal latch 74LS373. The binary code required to display a digit is determined by the type of the seven segments LED (common cathode or common anode) and the connections of the

data lines. For example, in Figure 5.6, to display digit I at the output port, seg­ments Band C should be turned on, and these segments are turned on with logic 0. Therefore, the binary code should be 79_H as follows:

The code for each Hex digit from 0 to F can be determined by examining the connections of the data lines to the segments and the logic requirements.

When the microprocessor executes the OUT instruction, the IOSEL goes active and enables (LE) the latch, and the code 79_H is passed on from the data bus to the latches. The output buffer of the latch is already enabled by grounding O͞E͞;thus, the code displays digit I at the seven-segment LED by turning on the segments B and C. The latch can sink 24 mA when the output logic is low; the current limiting resistors 330Ώ controls the current flow through the lighted segments. Now the question is, Why not use a common cathode LED? If a common-cathode seven segment LED is used in this circuit, the output of the latch would have to be high to drive the segments. The latch can supply approximately 2.6 mA when the output is high; this current is insufficient to drive the segments.

5.1.3 Basic Concepts in Interfacing Output Devices

The concepts in interfacing output devices are similar to those in interfacing mem­ory. The steps can be listed as follows:

1. Decode the low-order address bus to generate a unique pulse corresponding to the port address on the bus; this is called the I/O address (I͞O͞A͞D͞R͞) pulse.

2. Combine (AND) the I/O address pulse (I͞O͞A͞D͞R͞), I͞͞O͞R͞Q͞ , and W͞͞R͞ to generate the IOSEL (I/O select) pulse (Figure 5.2(a)). Another approach is to generate the I͞O͞W͞͞R͞ (I/O Write) by combining I͞͞O͞R͞Q͞ and W͞͞R͞, and then combine I͞O͞W͞͞R͞ with the I͞O͞A͞D͞R͞ (I/O Address) pulse to generate the IOSEL pulse (Figure 5.2(b)). The critical concept here is that the decoded address, I͞͞O͞R͞Q͞, and W͞͞͞R͞ are all necessary to latch the data at the appropriate time; how these signals are combined is often dictated by availability of decoding devices (chips) in the system.

3. Use the IOSEL pulse to enable (activate) the output device.

Let us examine the significance of the I/O select pulse. This pulse is gener­ated by ANDing the decoded address, I͞͞O͞R͞Q͞ , and W͞͞R͞ signals as shown in Figure 5.2(a); all these signals are active low. The assertion of this pulse indicates two pieces of information: (1) the low-order address bus has the port address (07_H), and (2) the data byte from the accumulator is on the data bus. Thus, this is the

appropriate time to enable the latch (or open the gate for data). Figure 5.2(b) shows how these control signals are generally ANDed in a typical interfacing circuit to generate the IOSEL pulse and how the I/O select pulse is used to enable the output latch.

Interfacing I/O Devices

The I/O (Input/Output) is the third component of a microprocessor-based system. I/O devices, such as keyboards and displays, are the ears and eyes of the MPUs; they are the communi­cation channels to the "outside world." Data can enter or exit in groups of eight bits using the entire data bus; this is called the parallel I/O mode. The other mode is the serial I/O, whereby one bit is transferred using one data line; typical examples include peripherals such as CRT ter­minals or cassette tapes. In this chapter, we fo­cus on interfacing I/O devices in the parallel mode; the serial mode will be discussed in the topic.

In the parallel I/O mode, devices can be interfaced using two techniques: peripheral mapped I/O and memory-mapped I/O. In peripheral-mapped I/O, a device is identified with an 8-bit address and enabled by I/O-related control signals. In memory-mapped I/O, a de­vice is identified with a 16-bit address and en­abled by memory-related control signals. The process of data transfer in both is identical. Each device is assigned a binary address through its interfacing circuit. When the Z80 is programmed to transfer data, it places the ap­propriate address on the address bus,

Sends the control signals, enables the interfacing device, and transfers data. The interfacing device is like a gate for data bits, which is opened by the MPU whenever it intends to transfer data.

To grasp the essence of interfacing tech­niques, we first examine the machine cycles of I/O instructions to determine the timings for I/O data arriving on the data bus, and then latch (or catch) that information.

We derive the basic concepts of peripheral-mapped and memory mapped I/O from the machine cycles. The peripheral-mapped I/O concepts are illustrated with two examples: interfacing LEDs as an output device and switches as an input device. The memory-mapped I/O technique is illustrated with an example of appliance control. The chapter also includes additional interfacing ex­amples that occur frequently in microprocessor based products.

OBJECTIVES:

· Illustrate the Z80 bus contents and control signals when OUT and IN instructions are executed.

· Explain the necessity of Wait states in I/O machine cycles.

· Recognize the device (port) address of a peripheral-mapped I/O by analyzing the as­sociated logic circuit.

· Recognize the device (port) address of a memory-mapped I/O by analyzing the asso­ciated logic circuit.

· Explain the differences between the periph­eral-mapped and memory-mapped I/O tech­niques.

· Interface an I/O device to the Z80 micropro­cessor for a specified device address by using logic gates and such MSI chips as decoders, latches; and buffers.

· Explain the concepts in interfacing analog devices such as sensors and motors.

INTERFACING OUTPUT DEVICES:

In peripheral-mapped I/O, a device is identified with an 8-bit address, and I/O ­related control signals are used to enable the device. The process of data transfer is in many ways similar to that of reading from or writing into a memory register. The Z80 uses the instruction IN to read (input) data from an input device and uses the instruction OUT to write (send) data to an output device. To understand in­terfacing of I/O devices, we need to examine the execution and machine cycles. Of these input/output instructions. In the next section, we will examine the exe­cution of the OUT instruction and discuss the interfacing of output devices, and in Section 5.3, we will examine the IN instruction and discuss the interfacing of input devices.

5.1.1 OUT Instruction

The Z80 microprocessor has several output instructions to send (copy or write) data to an output device. It can send data from the accumulator, internal general purpose registers, or memory registers to an output device. The Out instructions include the 8-bit address of a device as an operand. Therefore, the address can be any of the 256 8-bit binary combinations from OOH to FF_H• Thus, an output device can be assigned any 8-bit address between OO_H and FF_H through an appropriate interfacing circuit. The address range from OOH to FF_H is called the I/O or periph­eral map, and an address can be referred to as a device address, port address, or port number. Among the several Out instructions, we will examine the machine cycles and timing of the following instruction.

This is a 2-byte instruction with the hexadecimal opcode D3, and the second byte is the port ad­dress of an output device.

This instruction transfers (copies) data from the accumulator to the output device.

Typically, to display the contents of the accumulator at an output device (such as LEDs) with the address, for example, 07_H, the instruction will be written and stored in memory as follows:

When the microprocessor reads and executes the machine codes written at memory registers 2050_H and 2051_H, it will transfer (copy) the byte from the accu­mulator to the LED port with address 07_H and display the byte. Now the question remains: How is the address 07_H assigned to the output port? To answer that question, we need to examine the machine cycles of this instruction, as shown in the next section.

5.1.2 Execution of OUT Instruction and Timing

The OUT instruction has three machine cycles: Opcode Fetch, Memory Read, and I/O Write. The Z80 reads the opcode and the port address from memory in the first two machine cycles and writes into the port in the third cycle. Figure 5.1 shows the timing of the OUT instruction with the port address 07_H•

The first two machine cycles-Opcode Fetch and Memory Read-are simi­lar to the machine cycles shown in Figure 3.5; however, in Figure 5.1, the low order and high-order address buses are shown separately to illustrate the contents of the low-order bus in the third cycle. In the Opcode Fetch cycle, the Z80 places the address 2050_H on the address bus and fetches the opcode D3_H (1 1 0 I 00 1 1) via the data bus. When the Z80 decodes the opcode, it realizes that the instruction consists of two bytes, and that it must read the second byte. In the second ma­chine cycle, the Z80 places the next address, 2051_H, on the address bus and reads the port address 07_H•

In the third machine ‘cycle, M₃ (I/O Write), the following events occur:

1. The Z80 places the port address 07 _H on the low-order address bus and the contents of the accumulator on the data bus.

2. During T₂, it asserts the I͞͞O͞R͞Q͞ and ͞͞͞͞W͞͞R͞ control signals; the assertion of I͞͞O͞R͞Q͞ indicates that it is an I/O operation.

3. The Z80 automatically inserts a single Wait state Tw after T₂ to allow sufficient response time for an I/O device; this Wait state is added regardless of the WAIT signal status.

4. During T₃, the control signals I͞͞O͞R͞Q͞ and W͞͞R͞ become inactive.

To interface an output device, the information on the buses during the M₃ cycle is critical. From the beginning of T₂ until the end of T₃, we have the port address (07_H) on the low-order address bus and the data byte to be displayed on the data bus. The availability of this information is indicated by the control sig­nals. Now what we must do is to latch (catch) this information using the control signals before it disappears from the buses; we need to open the gate at that precise moment to let the data flow to the "outside world." This is the essence of interfacing.