Semiconductors:Semiconductor Failure Modes

Semiconductors

Introduction

The first line of defense in the protection of electronic equipment from damaging transient overvoltages is the ac-to-dc power supply. Semiconductor power-supply components are particularly vulnerable to failure from ac line disturbances. Devices occasionally will fail from one large transient, but many more fail because of smaller, more frequent spikes that punch through the device junction. Such occurrences explain why otherwise reliable systems fail “without apparent reason.”

Semiconductor Failure Modes

Semiconductor devices may be destroyed or damaged by transient disturbances in one of several ways. The primary failure mechanisms include:

• Avalanche-related failure

• Thermal runaway

• Thermal secondary breakdown

• Metallization failure

• Polarity reversals

When a semiconductor junction fails because of overstress, a low-resistance path is formed that shunts the junction. This path is not a true short, but it is a close approximation. The shunting resistance can be less than 10 Ω in a junction that has been heavily overstressed. By comparison, the shunting resistance of a junction that has been only mildly overstressed can be as high as 10 MΩ. The formation of low-resistance shunting paths is the result of the junction’s electrothermal response to overstress.

Device Ruggedness

The best-constructed device will fail if exposed to stress exceeding its design limits. The safe operating area (SOA) of a power transistor is the single most important parameter in the design of high-power semicon- ductor-based systems. Fortunately, advances in diffusion technology, masking, and device geometry have enhanced the power-handling capabilities of semiconductor devices.

A bipolar transistor exhibits two regions of operation that must be avoided:

Dissipation region — where the voltage-current product remains unchanged over any combination of voltage (V) and current (I). Gradually, as the collector-to-emitter voltage increases, the electric field through the base region causes hot spots to form. The carriers may punch a hole in the junction by melting silicon. The result is a dead (short-circuited) transistor.

Second breakdown (Is/b) region — where power transistor dissipation varies in a nonlinear inverse relationship with the applied collector-to-emitter voltage when the transistor is forward-biased.

To get SOA data into some type of useful format, a family of curves at various operating temperatures must be developed and plotted. This exercise gives a clear picture of what the data sheet indicates, compared with what happens in actual practice.

Forward Bias Safe Operating Area

The forward bias safe operating area (FBSOA) describes the ability of a transistor to handle stress when the base is forward-biased. Manufacturer FBSOA curves detail maximum limits for both steady-state dis- sipation and turn-on load lines. Because it is possible to have a positive base-emitter voltage and negative base current during the device storage time, forward bias is defined in terms of base current.

Bipolar transistors are particularly sensitive to voltage stress, more so than with stress induced by high currents. This situation is particularly true of switching transistors, and it shows up on the FBSOA curve. Figure 6.1 shows a typical curve for a common power transistor. In the case of the dc trace, the fol- lowing observations can be made:

• The power limit established by the bonding wire limit portion of the curve permits 135 W maximum dissipation (15 A × 9 V).

• The power limit established by the thermal limit portion of the curve permits (at the maximum voltage point) 135 W maximum dissipation (2 A × 67.5 V). There is no change in maximum power dissipation.

• The power limit established by the secondary breakdown portion of the curve decreases dramatically from the previous two conditions. At 100 V, the maximum current is 0.42 A, for a maximum power dissipation of 42 W.

Reverse Bias Safe Operating Area

The reverse bias safe operating area (RBSOA) describes the ability of a transistor to handle stress with its base reverse-biased. As with FBSOA, RBSOA is defined in terms of current. In many respects, RBSOA and FBSOA are analogous. First among these is voltage sensitivity. Bipolar transistors exhibit the same sensi- tivity to voltage stress in the reverse bias mode as in the forward bias mode. A typical RBSOA curve is shown in Figure 6.2. Note that maximum allowable peak instantaneous power decreases significantly as voltage is increased.

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Power-Handling Capability

The primary factor in determining the amount of power a given device can handle is the size of the active junction(s) on the chip. The same power output from a device can be achieved through the use of several smaller chips in parallel. This approach, however, may result in unequal currents and uneven distribution of heat. At high power levels, heat management becomes a significant factor in chip design.

Specialized layout geometries have been developed to ensure even current distribution through- out the device. One approach involves the use of a matrix of emitter resistances constructed so that the overall distribution of power among the parallel emitter elements results in even thermal dissipation. Figure 6.3 illustrates this interdigited geometry technique.

With improvements in semiconductor fabrication processes, output device SOA is primarily a function of the size of the silicon slab inside the package. Package type, of course, determines the ultimate dissipation because of thermal saturation with temperature rise. A good TO-3 or a two- screw-mounted plastic package will dissipate approximately 350 to 375 W if properly mounted. Figure 6.4 demonstrates the relationships between case size and power dissipation for a TO-3 package.

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Semiconductor Derating

Good engineering practice calls for a measure of caution in the selection and application of active devices. Unexpected operating conditions, or variations in the manufacturing process, can result in field failures unless a margin of safety is allowed. Derating is a common method of achieving such a margin. The primary derating considerations are:

Power derating — designed to hold the worst-case junction temperature to a value below the normal permissible rating.

Junction-temperature derating

an allowance for the worst- case ambient temperature or case temperature that the device is likely to experience in service.

Voltage derating — an allow- ance intended to compensate

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result of instantaneous peak-voltage excursions caused by transient disturbances.

Failure Mechanisms

It is estimated that as much as 95% of all transistor failures in the field are directly or indirectly the result of excessive dissipation or applied voltages in excess of the maximum design limits of the device. There are at least four types of voltage breakdown that must be considered in a reliability analysis of discrete power transistors. Although they are not strictly independent, each type can be treated separately. Keep in mind, however, that each is related to the others.

Avalanche Breakdown

Avalanche is a voltage breakdown that occurs in the collector-base junction, similar to the Townsend effect in gas tubes. This effect is caused by the high dielectric field strength that occurs across the collector-base junction as the collector voltage is increased. This high-intensity field accelerates the free charge carriers so that they collide with other atoms, knocking loose additional free charge carriers that, in turn, are accelerated and have more collisions.

This multiplication process occurs at an increasing rate as the collector voltage increases, until at some voltage, Va (avalanche voltage), the current suddenly tries to go to infinity. If enough heat is gener- ated in this process, the junction will be damaged or destroyed. A damaged junction will result in higher- than-normal leakage currents, increasing the steady-state heat generation of the device, which ultimately can destroy the semiconductor junction.

Alpha Multiplication

Alpha multiplication is produced by the same physical phenomenon that produces avalanche break- down, but differs in circuit configuration. This effect occurs at a lower potential than the avalanche volt- age and generally is responsible for collector-emitter breakdown when base current is equal to zero.

Punch-Through

Punch-through is a voltage breakdown occurring at the collector-base junction because of high collector voltage. As collector voltage is increased, the space charge region (collector junction width) gradually increases until it penetrates completely through the base region, touching the emitter. At this point, the emitter and collector are effectively short-circuited together.

Although this type of breakdown occurs in some PNP junction transistors, alpha multiplication breakdown generally occurs at a lower voltage than punch-through. Because this breakdown occurs between the collector and emitter, punch-through is more serious in the common-emitter or common- collector configuration.

Thermal Runaway

Thermal runaway is a regenerative process by which a rise in temperature causes an increase in the leak- age current; in turn, the resulting increased collector current causes higher power dissipation. This action raises the junction temperature, further increasing leakage current.

If the leakage current is sufficiently high (resulting from high temperature or high voltage), and the current is not adequately stabilized to counteract increased collector current because of increased leakage current, this process can regenerate to a point that the temperature of the transistor rapidly rises, destroy- ing the device. This type of effect is more prominent in power transistors, where the junction normally is operated at elevated temperatures and where high leakage currents are present because of the large junction area. Thermal runaway is related to the avalanche effect and is dependent upon circuit stability, ambient temperature, and transistor power dissipation.

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