Semiconductor failures caused by high-voltage stresses are becoming a serious concern for engineers, operators, and technical managers as new, high-density integrated circuits are placed into service. Internal IC connection lines that were 1.0 micron a few years ago have been reduced to well below 0.30 micron. Spacing between leads has been reduced by a factor of 4 or more. The most common microprocessors, and many other ICs, are manufactured using a planar process where a pure silicon wafer is selectively masked and diffused with chemicals to make multiple transistors. This combination is then selectively masked again, and metal is deposited on the wafer to interconnect the transistors . A decade ago, most integrated circuits used only one layer of metal; today, however, advanced microprocessors use multiple layers of metal to increase the packing density. A cross section of a five-layer microprocessor is shown in Figure 6.22.
As the geometries of the individual transistors are reduced, the propagation delays through the devices also become smaller. Unfortunately, as the metalized interconnects get smaller, their resistance and capacitance increases and, there- fore, the propagation delay through those inter- connects increases. As the semiconductor industry moves to still smaller geometries, the delay through the metal will become greater than the delay through the transistor itself. There are several approaches to this challenge — the most obvious being to use a metal with higher conductivity than aluminum (currently used in chip production). Copper offers some attractive solutions but is more difficult to process. Alter- native design techniques that use more transis- tors and fewer interconnects are also possible.
As the transistor count goes up, then so
does the power dissipation. More importantly, however, is the corresponding increase in frequency (power increases as the square of the frequency). The only variable that is changeable in the power equa- tion is the supply voltage — power dissipation also is proportional to the square of the voltage. This operating limitation is the reason for movement to low-voltage microprocessors and other logic devices.
In the past, the IC overvoltage peril was primarily to semiconductor substrates. Now, however, the metal- lization itself—the points to which leads connect — is subject to damage. Failures are the result of three primary overvoltage sources:
• External human-made — overvoltages coupled into electronic hardware from utility company ac power feeds, or other ac or dc power sources
• External natural — overvoltages coupled into electronic hardware as a result of natural sources
• Electrostatic discharge — overvoltages coupled into electronic hardware as a result of static generation and subsequent discharge
Most semiconductor failures are of a random nature. That is, different devices respond differently to a specific stress. Figure 6.23 illustrates how built-in (latent) defects in a given device affect the time-to-failure point of the component. Slight imperfections require greater stress than gross imperfections to reach a quantifiable failure mode.
Integrated circuits intended for computer applications have been a driving force in the semiconductor industry. Fig- ure 6.24 shows a simplified cutaway view of a DIP IC package. Connections between the die itself and the outside world are made with bonding wires. Figure 6.25 shows a cutaway view of a bonding pad.
Hybrid microcircuits also have become common in consumer and industrial equipment. A hybrid typically utilizes a number of components from more than one technology to perform a function that could not be achieved in monolithic form with the same performance, efficiency, or cost. A simple multi- chip hybrid is shown in Figure 6.26.
The effects of high-voltage breakdown in a hybrid semiconductor chip are illustrated graphically in Figure 6.27a to c. Failure analysis indicated that the pass transistor in this voltage regulator device was overstressed because of excessive input/output voltage differential.
With the push for faster and more complex ICs, it is unlikely that semiconductor manufacturers will return to thicker oxide layers or larger junctions. Overvoltage protection must come, instead, from circuitry built into individual chips to shunt transient energy to ground.
Most MOS circuits incorporate protective networks. These circuits can be made quite efficient, but there is a tradeoff between the amount of protection provided and device speed and packing density. Protective elements, usually diodes, must be physically large if they are to clamp adequately. Such elements take up a significant amount of chip space. The RC time constants of protective circuits also can place limits on switching speeds.
Protective networks for NMOS devices typically use MOS transistors as shunting elements, rather than diodes. Although diodes are more effective, fewer diffusions are available in the NMOS process, so not as many forward-biased diodes can be constructed. Off-chip protective measures, including electro- magnetic shielding, filters, and discrete diode clamping, are seldom used because they are bulky and expensive.
Figure 6.28 shows the protective circuitry used in a 54HC high-speed complementary metal-oxide silicon (CMOS) device. Polysilicon resistors are placed in series with each input pin, and relatively large- geometry diodes are added as clamps on the IC side of the resistors. Clamping diodes also are used at the output. The diodes restrict the magnitude of the voltages that can reach the internal circuitry. Protective features such as these have allowed CMOS devices to withstand ESD test voltages in excess of 2 kV.