Power MOSFETs (metal-oxide semiconductor field-effect transistors) have found numerous applications because of their unique performance attributes. A variety of specifications can be used to indicate the maximum operating voltages a specific device can withstand. The most common specifications include:
• Gate-to-source breakdown voltage
• Drain-to-gate breakdown voltage
• Drain-to-source breakdown voltage
These limits mark the maximum voltage excursions possible with a given device before failure. Excessive voltages cause carriers within the depletion region of the reverse-biased PN junction to acquire sufficient kinetic energy to result in ionization. Voltage breakdown also can occur when a critical electric field is reached. The magnitude of this voltage is determined primarily by the characteristics of the die itself.
Safe Operating Area
The safe dc operating area of a MOSFET is determined by the rated power dissipation of the device over the entire drain-to-source voltage range (up to the rated maximum voltage). The maximum drain-source voltage is a critical parameter. If exceeded even momentarily, the device can be damaged permanently.
Figure 6.5 shows a representative SOA curve for a MOSFET. Notice that limits are plotted for several parameters, including drain-source voltage, thermal dissipation (a time-dependent function), package capability, and drain-source on-resistance. The capability of the package to withstand high voltages is determined by the construction of the die, including bonding wire diameter, size of the bonding pad, and internal thermal resistances. The drain-source on-resistance limit is simply a manifestation of Ohm’s law; with a given on-resistance, current is limited by the applied voltage.
To a large extent, the thermal limitations described in the SOA chart determine the boundaries for MOSFET use in linear applications. The maximum permissible junction temperature also affects the pulsed current rating when the device is used as a switch. MOSFETs are, in fact, more like rectifiers than bipolar transistors with respect to current ratings; their peak current ratings are not gain-limited, but thermally limited.
In switching applications, total power dissipation comprises both switching losses and on-state losses. At low frequencies, switching losses are small. As the operating frequency increases, however, switching losses become a significant factor in circuit design. The switching safe operating area (SSOA) defines the MOSFET voltage and current limitations during switching transitions. Although the SSOA chart outlines both turn-on and turn-off boundaries, it is used primarily as a source for turn-off SOA data. As such, it is the MOSFET equivalent of the reverse-biased SOA curve of bipolar transistors. As with the RBSOA rating, turn-off SOA curves are generated by observing device performance as it switches a clamped inductive load. Figure 6.6 shows a typical SSOA chart for a family of MOSFET devices.
Figure 6.7 illustrates a FET device switching an inductive load in a circuit with no protection from fly- back (back-emf) voltages. The waveform depicts the turn-off voltage transient resulting from the load and the parasitic lead and wiring inductance. The device experiences an avalanche condition for about 300 ns at its breakdown voltage of 122 V. Placing a clamping diode across the inductive load suppresses most (but not all) of the transient. (See Figure 6.8.) The drain-to-source (Vds) voltage still will overshoot the supply rail by the sum of the effects of the diode’s forward recovery characteristics, the diode lead inductance, and the parasitic series inductances. If the series resistance of the load is small in comparison with its inductance, a simple diode clamp may allow current to circulate through the load-diode loop for a significant period of time after the MOSFET is turned off. When this residual current is unacceptable, a resistance can be inserted in series with the diode at the expense of increasing the peak flyback voltage seen at the drain.
Protecting the drain-source from voltage transients with a zener diode (a wideband device) is another simple and effective solution. Except for the effects of the lead and wiring inductances and the negligible time required to avalanche, the zener will clip the voltage transient at its breakdown voltage. A slow-rise-time transient will be clipped completely; a rapid-rise-time transient may momentarily exceed the zener breakdown. These effects are shown in Figure 6.9.
Figure 6.10 shows an RC clamp network that suppresses flyback voltages greater than the potential across the capacitor. Sized to sustain nearly constant voltage during the entire switch cycle, the capacitor absorbs energy only during transients and dumps that energy into the resistance during the remaining portion of the cycle.
A series RC snubber circuit is shown in Figure 6.11. Although the circuit effectively reduces the peak drain voltage, it is not as efficient as a true clamping scheme. Whereas a clamping network dissipates energy only during the transient, the RC snubber absorbs energy during portions of the switching cycle that are not overstressing the MOSFET. This configuration also slows turn-on times because of the additional drain-source capacitance that must be charged.
Historically, a MOSFET’s maximum drain-to-source voltage specification prohibited even instantaneous excursions beyond stated limits; the first power MOSFET devices were never intended to be
operated in avalanche. As is still the case with most bipolar transistors, avalanche limitations simply were not specified. Some devices happened to be rugged, whereas others were not. Manufacturers now have designed power MOSFET devices that are able to sustain substantial currents in avalanche at elevated junction temperatures. As a result, these “ruggedized” devices have replaced older MOSFETs in critical equipment.
MOSFET Failure Modes
The thermal and electrical stresses that a MOSFET device may experience during switching can be severe, particularly during turn-off when an inductive load is present. When power MOSFETs were introduced, it usually was stated that, because the MOSFET was a majority carrier device, it was immune to second- ary breakdown as observed in bipolar transistors. It must be understood, however, that a parasitic bipolar transistor is inherent in the structure of a MOSFET. This phenomenon is illustrated in Figure 6.12. The parasitic bipolar transistor can allow a failure mechanism similar to secondary breakdown. Research has shown that if the parasitic transistor becomes active, the MOSFET may fail. This situation is particularly troublesome if the MOSFET drain-source breakdown voltage is approximately twice the collector-emit- ter sustaining voltage of the parasitic bipolar transistor. This failure mechanism results, apparently, when the drain voltage snaps back to the sustaining voltage of the parasitic device. This negative resistance char- acteristic can cause the total device current to constrict to a small number of cells in the MOSFET struc- ture, leading to device failure. The precipitous voltage drop synonymous with secondary breakdown is a result of avalanche injection and any mechanism, electric or thermal, that can cause the current density to become sufficiently large for avalanche injection to occur.
The effects of the breakdown modes outlined manifest themselves in various ways on the transistor:
• Avalanche breakdown usually results in destruction of the collector-base junction because of excessive currents. This, in turn, results in an open between the collector and base.
• Breakdown due to alpha multiplication and thermal runaway most often results in destruction of the transistor because of excessive heat dissipation that shows up electrically as a short circuit between the collector and the emitter. This condition, which is most common in transistors that have suffered catastrophic failure, is not always detected easily. In many cases, an ohmmeter check may indicate a normal condition. Only after operating voltages are applied will the failure mode be exhibited.
• Punch-through breakdown generally does not cause permanent damage to the transistor; it can be a self-healing type of breakdown. After the overvoltage is removed, the transistor usually will operate satisfactorily.
Thermal Second Breakdown
Junction burnout is a significant failure mechanism for bipolar devices, particularly junction field-effect transistor (JFET) and Schottky devices. The junction between a P-type diffusion and an N-type diffusion normally has a positive temperature coefficient at low temperatures. Increased temperature will result in increased resistance. When a reverse-biased pulse is applied, the junction dissipates heat in a narrow depletion region, and the temperature in that area increases rapidly. If enough energy is applied in this process, the junction will reach a point at which the temperature coefficient of the silicon will turn negative. In other words, increased temperature will result in decreased resistance. A thermal runaway condition can then ensue, resulting in localized melting of the junction. If sustaining energy is available after the initial melt, the hot spot can grow into a filament short. The longer the energy pulse, the wider the resulting filament short. Current filamentation is a concentration of current flow in one or more narrow regions, which leads to localized heating.
After the transient has passed, the silicon will resolidify. The effect on the device can be catastrophic, or it can simply degrade the performance of the component. With a relatively short pulse, a hot spot can form, but not grow completely across the junction. As a result, the damage may not appear immediately as a short circuit, but manifest itself at a later time as a result of electromigration or another failure mechanism.
The smaller device geometry required by high-density integrated circuits has increased the possibility of metallization failure resulting from transient overvoltages. Metallization melt is a power-dependent failure mechanism. It is more likely to occur during a short-duration, high-current pulse. Heat generated by a long pulse tends to be dissipated in the surrounding chip die.
Metallization failure also can occur as a side effect of junction melt. The junction usually breaks down first, opening the way for high currents to flow. The metallization then heats until it reaches the melting point. Metallization failure results in an open circuit. A junction short circuit can, therefore, lead to an open-circuit failure.
Transient disturbances typically build rapidly to a peak voltage and then decay slowly. If enough induc- tance or capacitance is present in the circuit, the tail will oscillate as it decays. This concept is illustrated in Figure 6.13. The oscillating tail can subject semiconductor devices to severe voltage polarity reversals, forcing the components into or out of a conducting state. This action can damage the semiconductor junction or result in catastrophic failure.