Semiconductors:ESD Failure Modes

ESD Failure Modes

Low-power semiconductors are particularly vulnerable to damage from electrostatic discharges (ESDs). MOS devices tend to be more vulnerable than other components. The gate of a MOS transistor is especially sensitive to electrical overstress. Application of excessive voltage can exceed the dielectric standoff voltage of the chip structure and punch through the oxide, forming a permanent path from the gate to the semiconductor below. An ESD pulse of 25 kV usually is sufficient to rupture the gate oxide. The scaling of device geometry that occurs with large-scale integrated (LSI) or very large-scale integrated (VLSI) components complicates this problem. The degree of damage caused by electrostatic discharge is a function of the following parameters:

• Size of the charge, determined by the capacitance of the charged object Joules Device failure

• Rate at which the charge is dissipated, deter- mined by the resistance into which it is dis- charged Common techniques for controlling static problems include the following:

• Humidity control. Relative humidity (RH) of 50% or higher will greatly inhibit elec- trostatic problems. Too much humidity, however, can create corrosion problems and may make some paper products dimension- ally unstable. Most data processing equip- ment manufacturers recommend 40 to 60% RH.

• Conductive floor coverings. Careful selec- tion of floor surfaces will aid greatly in con- trolling ESD problems. Conductive synthetic rubber and other special-purpose floor coverings are ideal. Vinyl-asbestos is marginal. Nylon carpeting usually is unac- ceptable from an ESD standpoint.

• Static drain path. A static drain path from


• Ion generators. Localized, chronic static problems can be neutralized through the use of an ion generator. Such systems commonly are used in semiconductor assembly plants and in the printing industry to dissipate static charges.

Failure Mechanisms

Destructive voltages or currents from an ESD event can result in device failure because of thermal fatigue or dielectric breakdown. MOS transistors normally are constructed with an oxide layer between the gate conductor and the source-drain channel region, as illustrated in Figure 6.17 for a metal gate device and Figure 6.18 for a silicon gate device. Bipolar transistor con- struction, shown in Figure 6.19, is less sus- ceptible to ESD damage because the oxide is used only for surface insulation.


Oxide thickness is the primary factor in MOS ruggedness. A thin oxide is more susceptible to electrostatic punch-through, which results in a permanent low-resistance short-circuit through the oxide. Where pinholes or other weaknesses exist in the oxide, damage is possible at a lower charge level. Semiconductor manufacturers have reduced oxide thickness as they have reduced device size. This trend has



resulted in a significant increase in sensi- tivity to ESD damage.

Detecting an ESD failure in a complex device can present a significant challenge for quality control engineers. For example, erasable programmable read-only memory (EPROM) chips use oxide layers less than Immediate failure resulting from ESD exposure is easily determined: the device no longer works. A failed component can be removed from the subassembly in which it is installed, representing no further reli- ability risk to the system. Not all devices exposed to ESD, however, fail immediately. Unfortunately, there is little data dealing with the long-term reliability of devices that have survived ESD exposure. Some experts, however, suggest that two to five devices are degraded for every one that fails. Available data indicates that latent failures can occur in both bipolar and MOS chips and that there is no direct relationship between the susceptibility of a device to catastrophic failure and its susceptibility to latent failure. Dam- age can manifest itself in one of two primary mechanisms:

• Shortened lifetime, a possible cause of many infant mortality failures seen during burn-in

• Electrical performance shifts, many of which can cause the device to fail electrical limit tests

Case in Point

Figure 6.20 shows an electron microscope photo of a chip that failed because of an overvoltage condition. An ESD to this MOSFET damaged one of the metallization connection points of the device, resulting in catastrophic failure. Note the spot where the damage occurred. The objects in the photo that look like bent nails are actually gold lead wires with a diameter of 1 mil. By contrast, a typical human hair is about 3 mils in diameter. The original photo was shot at ×200 magnification. Figure 6.21 offers another view of the MOSFET damage point, but at ×5000. The character of the damage can be observed. Some of the aluminum metallization has melted and can be seen along the bottom edge of the hole.

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