The Significance of Bits and Bobs
Groupings of eight bits, which represent a symbol or a number, are usually referred to as bytes, and the grouping of four bits is, somewhat obviously, sometimes called a nibble (sometimes spelt nybble). Bytes can be assembled into larger structures, which
are referred to as words. Thus a three byte word will comprise 24 bits (though word is by now being used mainly to mean two bytes and DWord to mean four bytes). Blocks are the next layer of structure perhaps comprising 512 bytes (a common size for computer hard discs). Where the arrangement of a number of bytes fits a regular structure the term frame is used. We will meet other terms that describe elements of structure in due course.
Conventionally we think of bits, and their associated patterns and structures, as being represented by one of two voltage levels. This is not mandatory and there are other ways of representing the on/off nature of the binary signal. You should not forget alternatives such as the use of mechanical or solid state switches, presence or absence of a light,
polarity of a magnetic field, state of waveform phase, and direction of an electric current. The most common voltage levels referred to are those used in the common 74 X 00 logic families and are often referred to as TTL levels. A logic 0 (or low) will be any voltage that is between 0 and 0.8 V while a logic 1 (or high) will be any voltage between 2.0 V and the supply rail voltage, which will be typically 5.0 V. In the gap between 0.8 and 2.0 V the performance of a logic element or circuit is not reliably determinable as it is in this region where the threshold between low and high logic levels is located. Assuming that the logic elements are being used correctly, the worst-case output levels of the TTL families for a logic 0 is between 0 and 0.5 V and for a logic 1 is between 2.4 V and the supply voltage. The difference between the range of acceptable input voltages for a particular logic level and the range of outputs for the same level gives the noise margin. Thus for TTL families, the noise margin is typically in the region of 0.4 V for both logic low and logic high. Signals whose logic levels lie outside these margins may cause misbehavior or errors and it is part of the skill of the design and layout of such circuitry that this risk is minimized.
Logic elements made using CMOS technologies have better input noise margins because the threshold of a CMOS gate is approximately equal to half of the supply voltage.
Thus, after considering the inevitable spread of production variation and the effects of temperature, the available input range for a logic low (or 0) lies in the range 0 to 1.5 V and for a logic high (or 1) in the range of 3.5 to 5.0 V (assuming a 5.0-V supply). However, the output impedance of CMOS gates is at least three times higher than that for simple TTL gates and thus in a 5.0-V supply system interconnections in CMOS systems are more susceptible to reactively coupled noise. CMOS systems produce their full benefit of high noise margin when they are operated at higher voltages but this is not possible for CMOS technologies intended to be compatible with 74 X 00 logic families.