The 3-panel HTPS projector block diagram
Figure 19.16 shows a block diagram for a 3-panel HTPS projector. Inputs from PC via a VGA connection, component video or composite video (CVBS) together with stereo sound may be received and processed by the projector A/V section. External digital video signal from a TMDS receiver (or HDMI for HD operations) is fed directly into the image processor. Composite video/chrominance C is selected by the video switch and processed by the video decoder/comb filter and following interlace-to-progressive conversion passed on to the image processor or scalar. RGB input from a personal computer is first clamped and then converted into a digital format before going to the image processor. The purpose of the image processor is to rescale the image to the native res- olution of the LCD microdisplay. The output from the image processor is analogue RGB which are individually gamma corrected on their way to RGB digital-to-analogue converter (DAC) and sample-and-hold ICs. The sample-and-hold (S/H) captures the instantaneous analogue value of each RGB signal and feeds it into the appropriate LCD panel to set the pixel value. LCD panel level shifting is carried out under the direction of a timing chip.
The zoom and focus functions are controlled by the central processing unit (CPU) as instructed by the remote IR control or manual operation of the front panel. The CPU also controls the operation of the fan motors.
A typical optical control system is illustrated in Figure 19.17. An I2C- controlled I/O expander chip is used to control three separate motors: focus, zoom and lens. The expander received instructions from the CPU via the serial bus to send (+) or (-) control signals to the relevant motor drive IC (Figure 19.18).