THE I2C BUS
The simplicity of interfacing between the computer, memory and other chips described above is due to the use of a Philips-designed internal data-exchange system called Inter-IC (I2C) bus. A wide range of ICs, from colour and text decoders to audio amplifiers,
r.f. modulators and tuners, have unique addresses and I2C decoders to permit their control by automatic or manual means via the control microcomputer and, in the latter case, the user’s remote control handset. We have met several of them in previous chapters of this book. Unlike a true computer system, the control lines in a TV set are quiet for most of the time, so that an eight-wire paral- lel bus system would hardly be justified in terms of speed; it would also add greatly to the number of pins required on each IC (command and peripheral). The board area required for connections and chips, and the wire/plug/socket count would all increase, as would the cost, complexity and the risk of failure.
The I2C bus is a simple two-wire system, on which the data is sent in serial form. One line (data) is called SDA, and the other, carrying clock pulses for synchronisation, is called SCL. When the bus is not carrying information both lines are held at logic 1 by pull-up resistors to the +ve supply line. All devices connected to the I2C bus must have an open-drain or open-collector to be able to use the wired- AND function.
Although the TV control system described above has only one master in the control microcomputer, the I2C bus is arranged to be bi-directional and to permit the use of more than one master. The pulse generator is called the master, the sending unit is called the transmitter and the receiving unit the slave. The addressing procedure on the I2C bus is such that the first byte of data sent determines which slave has been selected by the master. The most significant seven bits of this byte hold the slave address, and the least significant bit indicates whether the data will be written to or read from the slave. If two masters attempt to use the bus simultaneously, an arbitration process is initiated, in which the master addressing the slave with lower address will predominate; when that transaction is complete, the second master is permitted use of the bus.
For each clock pulse on SCL there is a corresponding data pulse on SDA. The level must be stable on SDA when there is ‘1’ logic level on SCL, so that data on SDA may only be changed while SCL is at 0. The most significant bit is always sent first, and if SDA changes when SCL is at 1, either a start or stop condition is indicated, see Fig. 22.6. An example of I2C bus addressing and data from the microcomputer is given in Figs 22.6(b), (c) and (d). In Fig. 22.6(b) message start is signified by a drop to zero of SDA during an SCL ‘high’. Now comes the 7-bit chip address code 1100000 followed by a 0 to indicate that ‘write into colour decoder IC’ is required. This is now acknowledged by the slave IC, inviting further data. It comes in the form of a register address 00100010 which is the store for bright- ness information, Fig. 22.6(c), and its successful receipt is acknowledged on the next clock pulse after the 8-bit word. Finally the required brightness information (set by the user) is loaded into the selected register, overwriting the information already held. Here (Fig. 22.6(d)) the command is ‘full brightness’ corresponding to 00111111. It is loaded on the eight clock pulses of the word and acknowledged on the ninth. The stop (end of message) indication is given by SDA rising during SCL ‘high’. The new information in the brightness control data register raises the d.c. control voltage to the luminance clamp section of the colour decoder chip.
The ‘acknowledge’ procedure does not involve the direct transmis- sion of a pulse from slave to master; the ninth bit is passed out onto the bus by the master as a high (1) but held low (0) by the slave dur- ing the appropriate clock pulse if the preceding bits have been received. If the acknowledge bit is allowed to remain high, the master is thus informed that the data has not been accepted . . . or that no slave occupies the address given. All ‘TV-internal’ peripherals for use with the I2C bus have this acknowledge facility.