microcontrollers

is an introduction to Z80 assembly language programming. It explains commonly used instructions, elementary pro­gramming techniques and their applications, and the modular approach to software design.

The content is presented in a format sim­ilar to one for learning a foreign language. One approach to learning a foreign language is to be­gin with a few words that can form simple, meaningful, and interactive sentences. After learning a few sentences, one begins writing paragraphs that can convey ideas in a coherent fashion; then, by sequencing a few paragraphs, one can compose a letter. Chapters 6 to 11 are arranged in similar fashion-from simple in­structions to applications.

. Chapter 6 presents the Z80 programming model and provides an overview of the Z80 in­struction set and its capability. Chapter 7 deals with software development systems and Z80 as­semblers. Chapters 8 and 9 are concerned primarily with the Z80 instructions that occur most frequently. The instructions are not intro­duced according to the six groups as classified in Chapter 6; instead, a few instructions that can perform simple tasks are selected from each group. Chapter 8 includes the discussion of instructions from three groups–data copy. Arithmetic, and branch-and their various ap­plications. Chapter 9 introduces logic and bit manipulation instructions and their applica­tions. Chapter 10 introduces the concepts of subroutine and stack, which provide flexibility and variety for program design. Chapter 11 syn­thesizes the programming concepts presented in earlier chapters by illustrating application programs and demonstrates the modular ap­proach to software design.

PREREQUISITES

The reader is expected to know the following topics (refer to Chapters 1 and 2):

· Concepts in microprocessor architecture.

· Concepts related to memory and I/Os.

· Logic operations and binary and hexadeci­mal arithmetic.

ASSIGNMENTS

1. Explain why the number of output ports in peripheral-mapped I/O is re­stricted to 256 ports.

2. In peripheral-mapped I/O, can an input port and an output port have the same port address?

3. If an output and input port can have the same 8-bit address, how does the Z80 differentiate between the ports?

4. Specify the two control signals required to latch data in an output port.

5. Specify the type of pulse required to latch data in the 7475.

6. Are data latched in the 7475 at the leading edge, during the level, or at the trailing edge of the enable (E) signal?

7. If the control signals W̅R̅ and I̅O̅R̅Q̅ are asserted at the same time, can data be latched using only the control signal W̅R̅?

8. If the answer to the previous question is yes, what are potential problems with the interfacing circuit?

9. In Figure 5.4, explain why the LED cathodes rather than anodes are con­nected to the latch.

10. Specify the control signals required to enable an input port.

11. Explain why a latch is used for an output port, but a tri-state buffer can be used for an input port.

12. What are the control signals necessary in memory-mapped I/O?

13. Can the microprocessor differentiate whether it is reading from a memory ­mapped input port or from memory?

14. In Figure 5.11, connect the output of the comparator to data line D₇ and also drive the transistor with bit D₇ • Make the necessary changes in the instructions.

15. Identify the port address in Figure 5.13.

16. In Figure 5.13, if O̅E̅ is connected directly to the W̅R̅ signal and the output of the decoder is connected to the latch enable (through an inverter), can you display a byte at the output port? Explain your answer.

17. In Figure 5.14, determine whether it is the memory-mapped or the peripheral-mapped I/O.

18. In Figure 5.14, what is the port address if all the "don’t care" address lines are assumed to be at logic 0?

19. In Figure 5.15, are ports A and B input or output ports?

20. In Figure 5.15, what are the addresses of ports A and B?

21. In Figure 5.16, identify two output lines of decoder #2 that can be used as control signals and explain their functions. Explain why other output lines cannot be used as control signals.

22. In Figure 5.16, specify the I/O addresses.

23. In Figure 5.17, the decoder 74LS155 and an 8-input NAND gate are used to decode the address bus and generate the control signals. The decoder has two input lines (A₁ and A₀) and four enable lines (pins 1,2,14, and 15).

When pins 14 and 15 (active low) are enabled, the four output lines of the "b" group decode the input signal, and when pins 1 (active high) and2 (ac­tive low) are enabled, the four output lines of the "a" group decode the in­put signals. Identify the addresses that can assert the output lines of the de­coder and specify their I/O functions.

24. Sketch the waveforms of the M₁ cycles in the diagnostic routine (section 5.8).

25. Write a similar diagnostic routine to test the circuit in Figure 5.8

26. Is there a W̅R̅ pulse in your diagnostic routine of 25? If the answer is no, what is the unique identifiable signal that can be used to sync the scope?

SUMMARY

in this chapter, we have examined the machine cycles of the OUT and IN in­structions and derived the basic concepts for interfacing peripheral-mapped I/Os. Similarly, we examined the machine cycles of memory-related data trans­fer instructions and derived the basic concepts for interfacing memory-mapped I/Os. These concepts were illustrated with three examples of interfacing I/O de­vices and one example of interfacing an analog signal. The interfacing concepts can be summarized as follows.

Peripheral-Mapped I/O

· The OUT is a 2-byte instruction and copies (transfers or sends) data from the accumulator to the addressed port.

· When the Z80 executes the OUT instruction, in the third machine cycle it places the output port address on the low-order bus, places data on the data bus, and asserts the control signals I̅O̅R̅Q̅ and W̅R̅.

· A latch is generally used to interface output devices.

· The IN instruction is a two-byte instruction and copies (transfers or reads) data from an input port and places the data into the accumulator.

· When the Z80 executes the IN instruction, in the third machine cycle it places the input port address on the low-order bus, asserts the control signals I̅O̅R̅Q̅ and R̅D̅, and transfers data from the port to the accumulator.

· A tri-state buffer is generally used to interface input devices

· To interface an output or an input device, the low-order address bus needs to be decoded to generate the device address pulse, which must be combined with control signals I̅O̅R̅Q̅ and R̅D̅ (or W̅R̅) to select the device.

Memory-Mapped I/O

· Memory-related instructions are used to transfer data.

· To interface I/O devices, the entire bus must be decoded to generate the de­vice address pulse, which must be combined with the control signals M̅R̅E̅Q̅ and W̅R̅ or R̅D̅ to generate the I/O select pulse. Data are transferred by using this pulse to enable the I/O device.

5.9 SOME QUESTIONS AND ANSWERS

During the discussion of interfacing I/O devices, we focused on the basic concepts and avoided some details in order to simplify the presentation. We will now at­tempt to answer some of those questions.

1. What are the other I/O instructions in the Z80 instruction set, and how do they differ from the I/O instructions discussed here?

The Z80 instruction set includes six output instructions, of which we dis­cussed only one. The remaining five instructions perform various types of output functions: for example, output a byte from any of the registers or from a memory location, or output a block of memory. In these instructions, register C is used to specify the port address and register B can be used as a counter.

2. What are the contents of the high-order bus (A₁₅-A₈) during the M₃ cycle of the INIOUT instructions?

The contents of the high-order bus during the M₃ cycle of the I/O instruc­tions, illustrated in Sections 5.1 and 5.3, are generally irrelevant to the interfacing of I/O devices. For the I/O instructions discussed, the contents of the accumulator are placed on the A₁₅-A₈ bus. However, in other I/O instructions where the con­tents of register C are used to specify a port address, the contents of register B are placed on the high-order bus.

3. Why is one Wait state automatically inserted when an I/O instruction is executed?

When an I/O instruction is being executed, the control signal I̅O̅R̅Q̅ is as­serted during T₂, of the M₃ cycle. This does not leave sufficient time for the Z80 to sample the WAIT line. Therefore, a slow-responding I/O device would not be able to decode its address and activate the WAIT line if necessary. Adding one Wait cycle allows the device to activate the WAIT signal for additional Wait states.

4. In a memory-mapped I/O, what is the reason for not automatically inserting a Wait state?

In the Memory Read/Write cycles, the M̅R̅E̅Q̅ is asserted during T₁; there­fore, there is sufficient time to sample the WAIT line during T₂ state.

5. In a memory-mapped I/O, how does the microprocessor differentiate between I/O and memory, and can an I/O device have the same address as a memory register?

In the memory-mapped I/O, the microprocessor cannot differentiate be ­tween an I/O device and memory; it treats an I/O device as if it is memory. There­fore, an I/O device and memory register cannot have the same address; the entire memory map (64K) of the system has to be shared between memory and I/O.

6. Why is a I6-bit address (data) stored in memory in the reversed order, i.e., the low-order byte first, followed by the high-order byte?

In the Z80 microprocessor, the instruction decoder and the associated mi­croprogram are designed to recognize the second byte as the low-order byte in a 3-byte instruction.

5.8 TROUBLESHOOTING I/O INTERFACING CIRCUITS

In the last several sections, we discussed the interfacing of I/O devices and in­structions to test them. In I11ustrative Example 1(Figure 5.4), the test program includes two instructions that load the byte 97_H into the accumulator and output the byte to port 07_H• If we execute these instructions and no change is observed at the output port, we must implement the troubleshooting technique similar to that which we used for troubleshooting memory interfacing circuits in the last chapter. After checking the wiring and the pin connections, we can write a diag­nostic routine and execute it in a continuous loop to generate a constant and iden­tifiable signal, and then check various points in relation to that signal.

DIAGNOSTIC ROUTINE AND MACHINE CYCLES

We can use the same instructions for the diagnostic routine that we used in Illus­trative Example 1; however, to generate a continuous signal, we need to .add a Jump instruction, as shown.

This loop has 28 T-states and eight operations (machine cycles). To execute the loop once, the microprocessor asserts the R̅D̅ signal seven times (the Opcode Fetch is also a Read operation) and the W̅R̅ signal once. Assuming the system clock frequency is 2 MHz, the loop is executed in 14 µ_S, and the WR signal, repeated every 14µ_S, can be observed on a scope. If we sync the scope on the W̅R̅ pulse from the Z80, we can check the output of the 8-input NAND gate (I̅O̅A̅D̅R̅), I̅O̅W̅R̅, and I̅O̅S̅E̅L̅ signals; W̅R̅ and I̅O̅S̅E̅L̅ signals of a working circuit are shown in Figure 5.12.

When the Z80 asserts the W̅R̅ signal, the port address 07H must be on the address bus A₇-A_o, and the output of the NAND gate must be low. Similarly, the I̅O̅W̅R̅ must be low, and the IOSEL must be high. Now if we check the data bus in relation to the WR signal, one line at a time, we must read the data byte 97H.

5.7 ADDITIONAL ILLUSTRATIVE EXAMPLES:

INTERFACING SENSORS AND MOTORS

In previous examples, we illustrated the interfacing of I/O devices that were pri­marily binary devices (on/off). We now extend the concepts to interface analog devices such as temperature sensors and motors. In interfacing analog devices, the basic procedure remains similar to that of interfacing binary devices; the MPU identifies the device through a binary port address and enables it with an appro­priate control signal. However, we need to find a way to detect and to convert the analog signal into the binary format and vice versa. The analog signal is generally handled in two ways: one is to detect the signal when it reaches a predetermined level, and the other is to convert it into binary format proportional to its magni­tude. The predetermined level of the analog signal can be detected by using a comparator circuit, and the binary equivalent can be obtained by using an AID (Analog-to-Digital) data converter. In this section, we will focus on interfacing cir­cuits that can detect the predetermined level of analog signals and defer the dis­cussion of interfacing data converters to Chapter 13.

Figure 5.11 shows the interfacing of a temperature sensor. This circuit is designed to detect (through an input port) whether the temperature has risen to 100°C, and at that temperature it turns on the dc motor of a water pump. The de motor is interfaced with the MPU through an output port.

5.7.1 Hardware: Temperature Sensor LM135

And Comparator LM311

Figure 5.1l shows the LM 135 used as a temperature sensor. Its output is con­nected as one of the inputs to the comparator LM311. The LM135 is an integrated circuit, designed to sense changes in temperature; its output voltage changes 10 m V/ °C. It is rated to operate over a temperature range from – 55°C to + 150°C, and the current range 400 µA to 5 mA . At 25°C, the output of the sensor is typi­cally 2.98 V, and it increases I0mV/°C; therefore, at 100°C, it can reach 3.73 V (2.98 V + 750 mV).

The LM311 is a voltage comparator that can be operated from a + 5 V power Supply. The comparator compares two voltages at its input terminals, and if the difference between the two voltages is less than or equal to – 10 m V, its output remains at the saturation voltage of about 0.75 V; otherwise, the output is near the power supply voltage.

The output of the sensor is connected to the positive terminal of the com­parator, and its negative terminal is set to 3.73 V. At temperatures lower than 100°C the output voltage of the sensor is less than 3.73 V; thus, the comparator output remains at 0.75 V (logic 0). When the temperature reaches 100°C, the out­put of the sensor is 3.73 V, and the comparator output goes to + 4.5 V (logic I). The output of the comparator is connected to the tri-state buffer 74LS244, which serves as an input port to the MPU.

5.7.2 Interfacing Circuit for the Sensor

Figure 5.11 shows that the 74LS138 (3-to-8) decoder is used for address decoding. This decoding circuit is identical to the circuit shown in Figure 5.8; thus, the outputs of the decoder are asserted for port addresses ranging froin80_H to87_H ("don’t care" lines are assumed to be at logic 0). The control signals I̅O̅R̅D̅ (I/O’ Read) and I̅O̅W̅R̅ (I/O Write) are generated by using the 74LS139 (2-to-4) decoder; which is enabled by the I̅O̅R̅Q̅ signal. When the MPU intends to read, it asserts the I̅O̅R̅Q̅ and R̅D̅ signals. The input of the 2-to-4 decoder becomes 0 1, and the output O. goes active low to assert the IORD (I/O Read) control signal. The I̅O̅R̅D̅ is logically ANDed with the decoded address 80_H to generate the I̅O̅S̅E̅L̅_80H(I/O Select) signal, which enables the input buffer 74LS244 to read the output of the comparator. The output voltage of the comparator is connected to the data line Do through the buffer, and the MPU can monitor the temperature by monitoring the data line D₀ .

5.7.3 Interfacing Circuit for the DC Motor

The de motor is interfaced with the MPU through the latch 74LS373; the output bit O₀ of the latch can drive the de motor by turning on the transistor (Darlington pair). The logic level of bit O₀ of the latch is controlled by the data line D₀. The port address of the latch (87 _H) is determined by the 3-to-8 decoder; the output line O₇ of the decoder is ANDed with the control signal I̅O̅W̅R̅ to generate the IOSEL_87H, which enables the latch 74LS373. When the temperature reaches 100°C, the MPU sends logic I to the latch (port 87_H) to turn on the motor, and when the temperature is less than 100°C, the motor is turned off by the logic 0.

5.7.5 Program and Circuit Description

The first instruction IN A, (80H) enables the buffer 74LS244, reads the entire data bus D₇, D₀, and places the byte in the accumulator. However, we are interested in the logic level of only bit Do; it has the output of the comparator. Therefore, the next instruction ANDs the contents of the accumulator with the byte 01 _H in order to eliminate bits D₁-D₆ and save the logic level of bit D₀. When the temperature exceeds 100°C, the output of the comparator is about + 5 V, and the MPU reads logic 1 on the data line D₀. When the temperature is lower than 100°C, the com­parator output is about 0.7 V, and the MPU reads logic 0 on the data line D; The next instruction OUT turns on the transistor if D0 = 1 or turns off the transistor if D0 = 0. When the transistor is on, it supplies the necessary current for the motor to run, and when the transistor is off. The motor is turned off. The last instruction JP takes the program back to the beginning and continuously monitors the changes in the output of the comparator.

5.7.6 Additional Sensors and Output Devices

Figure 5. 11 illustrates one example of interfacing a sensor and driving a dc motor. We can extend the same concepts to other sensing and output devices. In Figure 5. 11, we used only one data line Do to monitor the output of the comparator. We can connect additional sensors such as light detectors, level detectors, and smoke detectors to the remaining data lines and instructions can monitor all the sensors in a sequence. Similarly, we can connect output devices such as speakers, alarms, and lights by using solid state relays to the remaining output lines of the latch.

5.5 MEMORY-MAPPED I/O

In, memory-mapped I/O, the input and output devices are assigned and identified by 16-bit addresses. To transfer data between the microprocessor and I/O devices, memory- related instructions (such as LD A, (16-bit) and memory control signals (such as M̅R̅E̅Q̅) are used. The microprocessor communicates with an I/O device as if it were one of the memory locations.

5.5.1 Memory-Related Data Transfer Instructions

To understand the memory-mapped I/O technique, we need to examine how a data byte is transferred from the Z80 to a memory location or vice versa. For example, the following instruction will transfer (copy) the contents of the accu­mulator to the memory location 8000_H• It is assumed here that the instruction is stored in memory locations 2050_H, 51_H, and 52_H•

This is a 3-byte instruction; the first byte is the opcode, and the second and the third bytes specify the memory address. However, the 16-bit address 8000_H is entered in the reverse order; the low-order byte 00 is stored in location 2051, followed by the high-order address 80_H (the reason for the reversed order will be explained in section 5.9).In this example, if an output device instead of a memory register is connected at this address, the accumulator contents will be transferred to the output device. This is called the memory-mapped I/O technique.

Similarly, the instruction LD A, (4000H) will transfer the contents of the memory location 4000_H to the accumulator. To assign this address for a memory ­mapped input port, we can interface an input device (for example a keyboard) instead of memory by using the memory-related control signals (MREQ and RD). When the processor executes the instruction, the accumulator receives data from the input device rather than from a memory register 4000_H•

5.5.2 Execution of Memory-Related Data Transfer Instructions

The execution of memory-related instructions discussed in the previous section is similar to the execution of I/O instructions (Sections 5.1 and 5.3), except that the memory-related instructions have 16-bit addresses. Figure 5.9 shows the execution of the instruction LD (8000H), A. It has four

machine cycles; in the first three machine cycles, the Z80 reads the three bytes. The fourth machine cycle M₄ (Memory Write) is similar to the machine cycle M₃ of the OUT instruction. In this machine cycle, the Z80 places the 16-bit address 8000_H on the address bus and the accumulator contents on the data bus. This is followed by the assertion of the control signals M̅R̅E̅Q̅ and W̅R̅ .The information available during M₄ can be used to interface a memory-mapped output port with the 16-bit address 8000_H•

In memory-mapped I/O, I/O selection and data transfer require steps similar to those required in peripheral-mapped I/O:

1. Decode the entire address bus A₁₅-A₀ (rather than just A₇-A₀ )

2. Combine the control signals M̅R̅E̅Q̅, W̅R̅, and the decoded pulse from Step 1 to generate a pulse similar to the M̅S̅E̅L̅ pulse, which will be used to select an I/O rather than memory.

3. Use the I/O select pulse (actually M̅S̅E̅L̅) to enable the I/O port.

To interface a memory-mapped input port, the steps are similar to those of the memory-mapped output port. We can use the instruction LD A, (16-bit), which reads data from an input port with the 16-bit address and places it in the accumulator. The instruction has four machine cycles; only the fourth machine cycle differs from M₄ in Figure 5.9. The control signal will be R̅D̅ rather than W̅R̅, and data flow from the input port to the microprocessor.