SUMMARY
in this chapter, we have examined the machine cycles of the OUT and IN instructions and derived the basic concepts for interfacing peripheral-mapped I/Os. Similarly, we examined the machine cycles of memory-related data transfer instructions and derived the basic concepts for interfacing memory-mapped I/Os. These concepts were illustrated with three examples of interfacing I/O devices and one example of interfacing an analog signal. The interfacing concepts can be summarized as follows.
Peripheral-Mapped I/O
· The OUT is a 2-byte instruction and copies (transfers or sends) data from the accumulator to the addressed port.
· When the Z80 executes the OUT instruction, in the third machine cycle it places the output port address on the low-order bus, places data on the data bus, and asserts the control signals I̅O̅R̅Q̅ and W̅R̅.
· A latch is generally used to interface output devices.
· The IN instruction is a two-byte instruction and copies (transfers or reads) data from an input port and places the data into the accumulator.
· When the Z80 executes the IN instruction, in the third machine cycle it places the input port address on the low-order bus, asserts the control signals I̅O̅R̅Q̅ and R̅D̅, and transfers data from the port to the accumulator.
· A tri-state buffer is generally used to interface input devices
· To interface an output or an input device, the low-order address bus needs to be decoded to generate the device address pulse, which must be combined with control signals I̅O̅R̅Q̅ and R̅D̅ (or W̅R̅) to select the device.
Memory-Mapped I/O
· Memory-related instructions are used to transfer data.
· To interface I/O devices, the entire bus must be decoded to generate the device address pulse, which must be combined with the control signals M̅R̅E̅Q̅ and W̅R̅ or R̅D̅ to generate the I/O select pulse. Data are transferred by using this pulse to enable the I/O device.