microcontrollers

10.6.1 Program Control Instructions

These instructions include branches, jumps, and subroutine calls as listed in Table 10.11.

Consider Bee d. There are 14 branch conditions. This means that the cc in Bee can be replaced by 14 conditions providing 14 instructions: BCC, BCS, BEQ, BGE, BGT, BHI, BLE, BLS, BLT, BMI, BNE, BPL, BVC, and BVS. It should be mentioned that some of these instructions are applicable to both signed and unsigned numbers, some can be used with only signed numbers, and some instructions are applicable to only unsigned numbers.

After signed arithmetic operations, instructions such as BEQ, BNE, BVS, BVC, BMI, and BPL can be used. On the other hand, after unsigned arithmetic operations, instructions such as BCC, BCS, BEQ, and BNE can be used. It should be pointed out that if V = 0, BPL and BGE have the same meaning, Likewise, if V = 0, BMI and BLT perform the same function.

The conditional branch instruction can be used after typical arithmetic instructions such as subtraction to branch to a location if cc is true. For example, consider SUB. W 01, 02. Now if [D1] and [D2] are unsigned numbers, then

Now as a specific example, consider BEQ BEGIN. If current [PC] = 000200 ₁₆, and BEGIN=$20 then, after execution of this BEQ, program execution starts at 000220 16 if Z = I; if Z = 0, program execution continues at 000200 ₁₆• The instructions BRA and JMP are unconditional jump instructions. BRA uses the relative addressing mode, whereas JMP uses only control addressing mode. For example, consider BRA.B START. If [PC]= 000200 ₁₆, and START=$40 then, after execution of this BRA, program execution starts at 000240 ₁₆• Now, consider JMP (Al) . If [Al] = 00000220 16, then, after execution of this JMP, program execution starts at 000220 ₁₆•

• The instructions BSR and JSR are subroutine call instructions. BSR uses the relative mode, whereas JSR uses the control addressing mode. Consider the following program segment: Assume that the main program uses all registers; the subroutine stores the result in memory.

Here, the JSR SUB instruction calls the subroutine SUB. In response to JSR, the 68000 pushes the current PC contents called START onto the stack and loads the starting address SUB of the subroutine into PC. The first MOVEM in the SUB pushes all registers onto the stack and, after the subroutine is executed, the second MOVEM instruction pops all the registers back. Finally, RTS pops the address START from the stack into PC, and program control in returned to the main program. Note that BSR SUB could have been used instead of JSR SUB in the main program. In that case, the 68000 assembler would have considered the SUB with BSR as a displacement rather than as an address with the JSR instruction.

• DBcc Dn, d tests the condition codes and the value in a data register. DBcc first checks if cc (NE, EQ, GT, etc.) is satisfied. If cc is satisfied, the next instruction is executed. If cc is not satisfied, the specified data register is decremented by I; if [Dn] = -1, then the next instruction is executed; on the other hand, if Dn ¢ -I, then branch to PC + d is performed. For example, consider DBNE. W DS, BACK with [D5] = 00003002 16, BACK= -4 and [PC] = 00200616• If Z = 1, then [D5] = 00003001 16• Because [D5] ¢ -I, program execution starts at 002002 16• It should be pointed out that there is a false condition in the DBcc instruction and that this instruction is the DBF (some assemblers use DBRA for this). In this case, the condition is always false. This means that, after execution of this instruction, Dn is decremented by I and if [Dn] = -I, then the next instruction is executed. If [Dn] ¢ -I, then branch to PC + d.

10.6.2 System Control Instructions

The 68000 system control instructions contain certain privileged instructions including RESET, RTE, STOP and instructions that use or modify SR. Note that the privileged instructions can be executed only in the supervisor mode. The system control instructions are listed in Table 10.12.

• The RESET instruction when executed in the supervisor mode outputs a low signal on the reset pin of the 68000 in order to initialize the external peripheral chips. The 68000 reset pin is bidirectional. The 68000 can be reset by asserting the reset pin using hardware, whereas the peripheral chips can be reset using the software RESET instruction.
• MOVE . L A 7 , An or MOVE . L An, A 7 can be used to save, restore, or change the contents of the A 7 in supervisor mode. A 7 must be loaded in supervisor mode because MOVE A 7 is a privileged instruction. For example, A7 can be initialized to $005000 in supervisor mode using MOVEA . L # $ 0 0 0 0 50 0 0 , A 1 MOVE.L Al,A7
• Consider TRAP #n. There are 16 TRAP instructions with n ranging from 0 to 15.

The hexadecimal vector address is calculated using the equation: Hexadecimal vector address= 80 + 4 x n. The TRAP instruction first pushes the contents of the PC and then the SR onto the stack. The hexadecimal vector address is then loaded into PC. TRAP is basically a software interrupt. The TRAP instruction can be used for service calls to the operating system. For application programs running in the user mode, TRAP can be used to transfer control to a supervisor utility program. RTE at the end of the TRAP routine can be used to return to the application program by placing the saved SR from the stack, thus causing the 68000 to return to the user mode.

There are other traps that occur due to certain arithmetic errors. For example, division by zero automatically traps to location 1416• On the other hand, an overflow condition (i.e., if V = 1) will trap to address 1C16 if the instruction TRAPV is executed.

• The CHK. W (EA), Dn instruction compares [Dn] with (EA). If [Dn]1ow 16 bits< 0 or if [Dn]_{1ow 16 bits} > (EA), then a trap to location 0018 16 is generated. Also, N is set to 1 if [Dn]_{10w 16 hits} < 0, and N is reset to 0 if [Dn]1ow 16 bits > (EA). (EA) is treated as a 16-bit twos complement integer. Note that program execution continues if [Dn]1ow 16 bits lies between 0 and (EA).

Consider CHK. W (AS), D2. If [D2]1ow 16 bits= 020016, [AS] = 00003000 ₁₆, and [003000 ₁₆] = 0100 ₁₆, then, after execution of this CHK, the 68000 will trap because  [D2] = 0200₁₆ is greater than [003000] = 0100₁₆•

The purpose of the CHK instruction is to provide boundary checking by testing if the content of a data register is in the range from zero to an upper limit. The upper limit used in the instruction can be set equal to the length of the array. Then, every time the array is accessed, the CHK instruction can be executed to make sure that the array bounds have not been violated.

The CHK instruction is usually placed after the computation of an index value to ensure that the index value is not violated. This permits a check of whether or not the address of an array being accessed is within array boundaries when address register indirect with index mode is used to access an array element. For example, the following instruction sequence permits accessing of an array with base address in A2 and array length of 50₁₀ bytes:

Here, if the low 16 bits of D2 are less than 0 or greater than 49, the 68000 will trap to location 0018 ₁₆• It is assumed that D2 is computed prior to execution of the CHK instruction.

10.6.3 68000 Stack

The 68000 supports stacks with the address register indirect postincrement and predecrement addressing modes. In addition to two system stack pointers (A7 and A7′), all seven address

registers (AO-A6) can be used as user stack pointers by using appropriate addressing modes. Subroutine calls, traps, and interrupts automatically use the system stack pointers: USP (A7) when S = 0 and SSP (A7′ ) when S = l. Subroutine calls push the PC onto the system stack; RTS pops the PC from the stack. Traps and interrupts push both PC and SR onto the system stack; RTE pops PC and SR from the stack.

The 68000 accesses the system stack from the top for operations such as subroutine calls or interrupts. This means that stack operations such as subroutine calls or interrupts access the system stack automatically from HIGH to LOW memory. Therefore, the system SP is decremented by 2 for word or 4 for long word after a push and incremented by 2 for word or 4 for long word after a pop. As an example, suppose that a 68000-CALL instruction (JSR or BSR) is executed when PC = $0031F200; then, after execution of the subroutine call, the stack will push the PC as follows:

In 68000, stacks can be created by using address register indirect with postincrement or predecrement modes. Typical 68000 memory instructions such as MOVE to/from can be used to access the stack. Also, by using one of the seven address registers (AO-A6) and system stack pointers (A7,A7′), stacks can be filled from either HIGH to LOW memory or vice versa:

1. Filling a stack from HIGH to LOW memory (Top of the stack) is implemented with predecrement mode for push and postincrement mode for pop.

2. Filling a stack from LOW to HIGH (Bottom of the stack) memory is implemented with postincrement for push and predecrement for pop.

For example, consider the following stack growing from HIGH to LOW memory addresses in which A7 is used as the stack pointer:

The 16-bit data item 050416 can be popped from the stack into the low 16 bits of D0 by using MOVE. W (A 7) +,D0. Register A 7 will contain 200504 ₁₆ after the pop. Note that, in this case, the stack pointer A7 points to valid data. Next, consider the stack growing from LOW to HIGH memory addresses in which the user utilizes A6 as the stack pointer:

To push the 16-bit contents 2070 16 of the low 16 bits ofD5, the instruction MOVE. w DS, (A 6} + can be used as follows. The 16-bit data item 2070 16 can be popped from the stack into the 16-bit contents of memory location 417024 16 by using MOVE. W – (A6) ,$  417 0 2 4. Note that, in this case, the stack pointer A6 points to the free location above the valid data.

10.6.1 Logical Instructions

These instructions include logical OR, EOR, AND, and NOT as shown in Table 10.7.

• Consider AND. B # $8 F, DO . If prior to execution of this instruction, [DO.B] = $72, then after execution of AND. B # $ 8 F, D0, the following result is obtained:

Z = 0 (Result is nonzero) and N = 0 (Most Significant Bit of the result is 0). C and V are always cleared to 0 after logic operation. The condition codes are similarly affected after execution of other logical instructions such as OR, EOR, and NOT. The AND instruction can be used to perform a masking operation. If the bit value in a particular bit position is desired in a word, the word can be logically ANDed with appropriate data to accomplish this. For example, the bit value at bit 2 of an 8- bit number 0100 IY10 (where unknown bit value ofY is to be determined) can be obtained as follows:

If the bit value Y at bit 2 is 1, then the result is nonzero (Flag Z=O); otherwise, the result is zero (Z= 1) . The Z flag can be tested using typical conditional ru MP instructions such as BEQ (Branch if Z= 1) or BNE (Branch if Z=O) to determine

whether Y is 0 or I. This is called masking operation. The AND instruction can also be used to determine whether a binary number is ODD or EVEN by checking the Least Significant bit (LSB) of the number (LS8=0 for even and LS8=1 for odd).

• Consider AND. W Dl, DS. If [Dl.W] = 0001 16 and [D5.W) = FFFF 16, then, after execution of this AND, the low 16 bits of both Dl and D5 will contain 0001 16•
• Consider ANDI .B #$00, CCR. If[CCR) = 01 16, then, after this ANDI, register CCR will contain 00₁₆•
• Source (EA) in AND and OR can use all modes except An .
• Destination (EA) in AND or OR or EOR can use all modes except An, relative, and immediate.
• Destination (EA) in ANDI, 0RI, and EORI can use all modes except An, relative, and immediate.
• (EA) in NOT can use all modes except An, relative, and immediate .
• Consider E0R. W # 2, DS . If prior to execution of this instruction, [ DS. W J $2 3 4 2, then after execution of EOR. W # 2, D 5, low 16-bit contents of D5 will be $ 2 3 4 0. All condition codes are affected in the same manner as the AND instruction. The Exclusive-OR instruction can be used to find the ones complement of a binary number by XORing the number with ali i’s as follows:

execution of this EOR, register D2.W will contain 0000 16, and Dl will remain unchanged at FFFF ₁₆•

• Consider NOT. B 05. If [D5.B] = 02 16,then, after execution of this NOT, the low byte ofD5 will contain FD ₁₆•

• Consider OR. B 02, D3 . If prior to execution of this instruction, [D2.B] = A2 ₁₆ and lD3.B] = 5D16, then after exection of OR. B 02, 03, the contents of D3.B are FFH. All flags are affected similar to the AND instruction. The OR instruction can typically be used to insert a 1 in a particular bit position of a binary number without changing the values of the other bits. For example, a 1 can be inserted using the OR instruction at bit number 3 of the 8-bit binary number 0 1 1 1 0 0 1 1 without changing the values of the other bits as follows:

• Consider ORI #$1002, SR. If [SR] = 111D16, then after execution of this ORI, register SR will contain lllF16• Note that this is a privileged instruction because the high byte of SR containing the control bits is changed and therefore, can be executed only in the supervisor mode.

10.6.2 Shift and Rotate Instructions

The 68000 shift and rotate instruction are listed in Table I0.8.

• All the instructions in Table 10.8 affect Nand Z flags according to the result. Vis reset to zero except for ASL.

• Note that in the 68000 there is no true arithmetic shift left instruction. In true arithmetic shifts, the sign bit of the number being shifted is retained. In the 68000, the instruction ASL does not retain the sign bit, whereas the instruction ASR retains the sign bit after performing the arithmetic shift operation.

• (EA) in ASL, ASR, LSL, LSR, ROL, ROR, ROXL, and ROXR can use all modes except Dn, An, relative, and immediate.

• Consider ASL. W Dl, 05. If [D1]_{1ow 16 bits} = 0002 ₁₆ and [D5]_{1ow 16 bits} = 9FF0 ₁₆, then, after this ASL instruction, [D5]10w l6bits = 7FC016, C = 0, and X= 0. Note that the sign of the contents of D5 is changed from 1 to 0 and, therefore, the overflow is set. The sign bit of D5 is changed after shifting [D5] twice. For ASL, the overflow flag is set to one if the sign bit changes during or after shifting. The contents of D5 are not updated after each shift. The ASL instruction can be used to multiply a signed number by 2" by shifting the number n times to the left; the result is correct if V = 0 while the result is incorrect if V = 1. Since execution time of the multiplication instruction is longer, multiplication by shifting may be more efficient when multiplication of a signed number by 2" is desired.

• ASR retains the sign bit. For example, consider ASR. W #2, Dl. If[D1.W] = FFE2 16, then, after this ASR, the low 16 bits of [D1] = FFF8 16, C = 1, and X = 1. Note that the sign bit is retained.

• ASL (EA) or ASR (EA) shifts (EA) 1 bit to left or right, respectively. For example, consider ASL. W (AO). If [AO] = 00002000 16 and [00200016] = 9001 16, then, after execution of this ASL, [00200016] = 2002 16, X= 1, and C = 1. On the other hand, after ASR. w (AO), memory location 002000 16 will contain C80016, C = 1, and X= I.

• The LSL and ASL instructions are the same in the 68000 except that with the ASL, V is set to 1 if the sign of the result is changed from the sign of the original value during or after shifting. This will allow one to multiply a signed number by 2" by shifting the number n times to left; the result is correct if V = 0 while the result is incorrect if V = 1. Since execution time of the multiplication instruction is longer, multiplication by shifting may be more efficient when multiplication of a signed number by 2" is desired.

• (EA) in the above instructions can use all modes except An, relative, and immediate.
• If (EA) is memory location then data size is byte: if (EA) is Dn then data size is long word.
• Consider LSR. W # 3, 01. If [Dl.W] = 800016,then after this LSR, (Dl.W] = 100016, X= 0, and C = 0.
• Consider ROL. B #2, 02. If [D2.B] = B1 16 and C = 1, then, after this ROL, the low byte of [D2] = C616 and C = 0. On the other hand, with [D2.B] = B 116 and C = I, consider ROR. B # 2, 02. After this ROR, low byte of register D2 will contain 6C 16 and C =0.
• Consider ROXL. W 02, 01. If [D2.W] = 000316, [Dl.W] = F201 16, C = 0, and X= I then after execution of this ROXL, [D1.W] = 900F16, C = I, and X = 1.

10.6.3 Bit Manipulation Instructions

The 68000 has four bit manipulation instructions, and these are listed in Table 10.9.

• In all of the instructions in Table 10.9, the ones complement of the specified bit is reflected in the Z flag. The specified bit is ones complemented, cleared to 0, set to I, or unchanged by BCHG, BCLR, BSET, or BTST, respectively. In all the instructions in Table 10.9, if(EA) is Dn, then the length of Dn is 32 bits; otherwise, the length ofthe destination is one byte memory.
• Consider BCHG. B #2, $0 03 0 0 0. If [003000 16] = 05 16, then, after execution of this BCHG, Z = 0 and [00300016] = 01 16•
• Consider BCLR. L # 3, 01. If [Dl] = F210E128 16, then after execution of this BCLR, register D1 will contain F210E120 16 and Z = 0.
• Consider BSET. B #0, (Al). If[AI]= 00003000 16 and [00300016] = 0016, then, after execution of this BSET, memory location 003000 16 will contain 01 16 and Z = 1.
• Consider BTST. B #2, $0 02 0 0 0. If [002000 16] = 02 16, then, after execution of this BTST, Z = 1, and [00200016] = 02 16; no other flags are affected.

10.6.4 Binary-Coded-Decimal Instructions

The 68000 instruction set contains three BCD instructions, namely, ABCD for adding, SBCO for subtracting, and NBCO for negating. They operate on packed BCD byte(s) and provide the result containing one packed BCD byte. These instructions always include the

extend (X) bit in the operation. The BCD instructions are listed in Table 10.10.

• Consider ABCO.B D1, D2. If[Dl.B] = 25 ₁₀, [D2.B] = 15₁₀, and X= 0, then, after execution of this ABCO instruction, [D2.B] = 4010, X= 0, and Z = 0.
• Consider SBCO. B – (A2) , – (A3). If [A2] = 00002004 16, [A3] = 00003003 ₁₆, [002003 16] = 0510, [003002 16] = 06₁₀, and X= 1, then after execution of this SBCD instruction, [00300216] = 0010, X = 0, and Z = 1.
• Consider NBCO. B (Al). If[A1] = [0000300016], [00300016] =0510, and X= 1, then, after execution of this NBCO instruction, [00300016] = -6₁₀ •

Note that packed BCD subtraction used in the instructions SBCO and NBCO can be obtained

by using the concepts discussed in Chapter 2 (Section 2.5.2).

10.7 68000 Delay Routine

Typical 68000 software delay l00ps can be written using MOVE and DBF instructions. For example, the following instruction sequence can be used for a delay l00p of 2 millisecond:

Note that DBF.W in the above decrements D0 .W by one, and if DO.W "’ -1 branches to DELAY; ifDO.W = -1, the 68000 executes the next instruction. Since DBF.W checks for DO.W for -1, the value of "count" must be one less than the required l00p count. The initial l00p counter value of "count" can be calculated using the cycles (Appendix D)

required to execute the following 68000 instructions:

DBF.W requires IO cycles when the 68000 branches if the content of D0.W is not equal to -1after autodecrementing D0.W by I. However, the 68000 goes to the next instruction and does not branch when [D0.W] = -1 after autodecrementing DO.W by 1, and this requires 14 cycles. This means that the DELAY l00p will require 10 cycles for "count" times, and the last iteration will take I4 cycles.

As before, assuming 4-MHz 68000 clock, each cycle is 250ns. Total time from the above instruction sequence for two-second delay= Execution time for MOVE.W + 1000 * (2 msec delay)+ 1000 *(Execution time for SUBQ.W) + 999* (Execution time for BNE.B for Z = 0 when Dl ..- 0) +(Execution time for BNE.B for Z = 1 when D1 = 0 for last iteration) = 8 * 250ns + I 000 * 2msec + 1000 * 4 * 250ns + 999 * 10 * 250ns + 8 * 250ns = 2.0035 seconds which is approximately 2 seconds discarding the execution times of MOVE.W, SUBQ.W, and BNE.B.

Example 10.1

Determine the effect of each of the following 68000 instructions:

• CLR D0
• MOVE. L D1, D0
• CLR.L (A0) +
• MOVE -(A0), D0
• MOVE 20 (A0 ), D0
• MOVEQ.L #$D7, D0
• MOVE 21 (A0, Al.L), D0

Assume the following initial configuration before each instruction is executed; also assume all numbers in hex:

Example 10.2

Write a 68000 assembly language program that implements each of the following C language program segments:

where sum is the address of the 16-bit result of addition.

ii) Write a 68000 assembly language program to find (X2) I (3276510) where X is a 16-bit signed number stored in D0.W. Store the 32-bit result (quotient and remainder) onto the user stack.

iii) What are the remainder, quotient, and register containing them after execution of the following 68000 instruction sequence?

Note that, in the above condition Fin DBF is always false. Hence, the program exits from the LOOP when D I= -1. Therefore, the addition process is performed 10 times.

Example 10.3

Write a 68000 assembly program at address $002000 to clear l 0010 consecutive bytes (from low to high addresses) to zero starting at location $003000.

Solution

No warnings generated

Note that the 68000 has no HALT instruction .. Therefore, the unconditional jump to the same location such as FINISH JMP FINISH is normally used at the end of the program. Because DBF is a word instruction and considers D0’s low 16-bit word as the l00p count, one should be careful about initializing D0 using MOVEQ. L #d8, Dn since this instruction sign extends low byte of Dn to 32 bits.

Example 10.4

Write a 68000 assembly language program at address $001000 to compute where

X₁. and Y_i are signed 16-bit numbers and N = 100. Store the 32-bit result in D 1. Assume that the starting addresses of X. and Yj are 100₁₆ and 200₁₆ respectively.

Example 10.5

Write a 68000 subroutine to compute Y = . Assume the X.’s are 16-bit signed integers and N = 100. The numbers are stored in consecutive locations. Assume A0 points to the X/s and A7 is already initialized in the main program. Store 32-bit result in D1 (16-bit remainder in high word of Dl and 16-bit quotient in the low word of Dl). Assume user mode.

In the above program, DIVU is used for computing LXi2/N since both SUM (Xi**2) and N=I00 are unsigned (positive). Note that in order to execute the above program, values for must be stored in memory using assembler directive, DC.W.

Example 10.6

Write a 68000 assembly language program at address 0 to move a block of 16-bit data of length I 0010 from the source block starting at location 002000 16 to the destination block starting at location 003000 16 from low to high addresses.

Solution

Note: Typical assemblers assemble a program starting at address 0 if assembler directive ORG is not used at the beginning of the program.

Example 10.7

Write a 68000 assembly language program at address 0 to add two words, each containing two ASCII digits. The first word is stored in two consecutive locations (from LOW to HIGH) with the low byte pointed to by A0 at address 000300 ₁₆, and the second word is stored in two consecutive locations (from LOW to HIGH) with the low byte pointed to by AI at 000700 ₁₆• Store the packed BCD result in D₅.

Solution

Example 10.8

Write a 68000 assembly language program that will perform : 5 x X+ 6 x Y + [Y/8] [ D l.L] where X is an unsigned 8-bit number stored in the lowest byte of D0 and Y is a 16-bit signed number stored in the upper 16 bits of D I.Neglect the remainder of Y/8.

Solution

Example 10.9

Write a 68000 assembly language program to convert temperature from Fahrenheit to Celsius using the following equation: C = [(F- 32)/9] x 5 ; assume that the low byte of D0 contains the temperature in Fahrenheit. The temperature can be positive or negative. Store result in D0.

Solution

Example 10.10

Write a 68000 assembly language program at address $4000 to add four 32-bit numbers stored in consecutive locations starting at address $3000. Store the 32-bit result onto the user stack. Assume that no carry is generated due to addition of two consecutive 32-bit numbers and A7 is already initialized.

Solution

Example 10.11

Write a subroutine in 68000 assembly language to implement the C language assignment statement: p = p + q; where addresses p and q hold two 16-digit (64-bit) packed BCD numbers (Nl and N2). The main program will initialize addresses p and q to $002000 and $003000 respectively. Address $002007 will hold the lowest byte ofNl with the highest byte at address $002000 while Address $003007 will contain the lowest byte of N2 with the highest byte at address $003000. Also, write the main program at address $004000 which will perform all initializations including address p (pointer AO to $002000), address q (pointer AI to $003000), l00p count (D1 to 7), and then call the subroutine at $008000 and stop. The subroutine will accomplish the task with the initialized values of AO, A I, and D1 in the main program. Use ABCD.B for BCD addition with predecrement mode. Assume supervisor mode. Note that the 68000 supervisor stack pointer is initialized upon hardware reset.

Solution

Examule 10.12

Write a 68000 assembly program to multiply an 8-bit signed number in the low byte ofDI by a 16-bit signed number in the high word ofD5. Store the result in D3.

Solution

Examule 10.13

Write a 68000 assembly language program at address $2000 to add ten 32-bit numbers stored in consecutive locations starting at address $502040. Initialize A6 to $00200504 and use the low 24 bits of A6 as the stack pointer to push the 32-bit result. Use only ADDX instruction for adding two 32-bit numbers each time through the l00p. Assume that no carry is generated due to the addition of two consecutive 32-bit numbers; this will provide the 32-bit result. This example illustrates use of the 68000 ADDX instruction.

Solution

Note that ADDX adds the contents of two data registers or the contents of two memory locations using predecrement modes.

Example 10.14

Write a 68000 assembly language program at address $2000 to subtract two 32-bit packed BCD numbers. The BCD number 1 is stored at the locations starting from $003000 through $003003, with the least significant byte at $003003 and the most significant byte at $003000. Similarly, the BCD number 2 is stored at the locations starting from $004000 through $004003, with the least significant byte at $004003 and the most significant byte at $004000. The BCD number 2 is to be subtracted from BCD number 1. Store the packed BCD result at addresses $005000 (Lowest byte of the result) through $005003 (Highest byte of the result). In the program, first initialize l00p counter D7 to 4, source pointer AO to $003000, source pointer A I to $004000, destination pointer A3 to $005000, and then write the program to accomplish the above using these initialized values.

Solution

Note that SBCD subtracts the contents of two data registers or the contents of two memory locations using predecrement modes.

Example 10.15

Write a 68000 assembly program at address $1000 which is equivalent to the following C language segment:

Assume that the arrays, x[i] and y[i] contain unsigned 16-bit numbers already stored in memory starting at addresses $3000 and $4000 respectively. Store the 32-bit result at address $5000.

10.5 Functional Categories Of 68000 Addressing Modes

All of the 68000 addressing modes in Table 10.2 can be further divided into four functional categories as shown in Table 10.3.

• Data Addressing Mode. An addressing mode is said to be a data addressing mode if it references data objects. For example, all 68000 addressing modes except the address register direct mode fall into this category.

• Memory Addressing Mode. An addressing mode capable of accessing a data item stored in memory is classified as a memory addressing mode. For example, the data and address register direct addressing modes cannot satisfy this definition.

• Control Addressing Mode. This refers to an addressing mode that has the ability to access a data item stored in memory without the need to specify its size. For example, all 68000 addressing modes except the following are classified as control addressing

modes: data register direct, address register direct, address register indirect with postincrement, address register indirect with predecrement, and immediate.

• Alterable Addressing Mode. If the effective address of an addressing mode is written into, then that mode is an alterable addressing mode. For example, the immediate and the program counter relative addressing modes will not satisfy this definition.

10.6 68000 Instruction Set

The 68000 instruction set contains 56 basic instructions. Table 10.4 lists some of the instructions affecting the condition codes. Appendices D and G provide the 68000 instruction execution times and the instruction set (alphabetical order), respectively.

The 68000 instructions can be classified into eight groups as follows:

• (EA) in LEA (EA), An can use all addressing modes except Dn, An, (An)+,- (An), and immediate.

• Destination (EA) in MOVE (EA), (EA) can use all modes except An, relative, and immediate.

• Source (EA) in MOVE (EA), (EA) can use all modes .

• Destination (EA) in MOVEM reg list, (EA) can use all modes except, An, (An)+, relative, and immediate.

• Source (EA) in MOVEM (EA), reg list can use all modes except Dn, An,- (An), and immediate.

• (EA) in PEA (EA) can use all modes except, An, (An)+, -(An), and immediate .

1. Data movement instructions

2. Arithmetic instructions

3. Logical instructions

4. Shift and rotate instructions

5. Bit manipulation instructions

6. Binary-coded decimal instructions

7. Program control instructions

8. System control instructions

10.6.1 Data Movement Instructions

These instructions allow data transfers from register to register, register to memory, memory to register, and memory to memory. In addition, there are also special data movement instructions such as MOVEM (move multiple registers). Typically, byte, word, or long word data can be transferred. A list of the 68000 data movement instructions is given in Table

10.5. Let us now explain the data movement instructions.

MOVE Instructions

The format for the basic MOVE instruction is MOVE. S (EA), (EA), where S = L, W, or B. (EA) can be a register or memory location, depending on the addressing mode used. Consider MOVE. B 03, 01, which uses the data register direct mode for both the source and destination. If [D3.B] = 0516 and [D l.B] = 01 16, then, after execution of this MOVE instruction, [Dl.B] = 05₁₆ and [D3.B] = 05₁₆•

There are several variations of the MOVE instruction. For example MOVE. W CCR, (EA) moves the contents of the low-order byte of SR (i.e., CCR) to the low-order byte of the destination operand; the upper byte of SR is considered to be zero. The source operand is a word. Similarly, MOVE. W (EA), CCR moves an 8-bit immediate number, or low-order 8-bit data, from a memory location or register into the condition code register; the upper byte is ignored. The source operand is a word. Data can also be transferred between (EA) and SR r USP (A7) using the following privileged instructions:

MOVEA. W or. L (EA), An can be used to load an address into an address register. Word-size source operands are sign-extended to 32 bits. Note that (EA) is obtained by using an addressing mode. As an example, MOVEA. W # $ 2 0 0 0, AS moves the 16-bit word 2000 16 into the low 16 bits of AS and then sign-extends 2000 16 to the 32-bit number 00002000 ₁₆• Note that sign extension means extending bit 15 of 2000 16 from bit 16 through bit 31. As mentioned before, sign extension is required when an arithmetic operation between two signed binary numbers of different sizes is performed. The (EA) in MOVEA can use all addressing modes.

The MOVEM instruction can be used to push or pop multiple registers to or from the stack. For example, MOVEM.L 00-07 /AO-A6,- (SP) saves the contents of all eight data registers and seven address registers in the stack. This instruction stores address registers in the order A6-AO first, followed by data registers in the order D7-DO, regardless of the order in the register list. MOVEM .L ( sP) +, DO-D7 I A 0-A 6 restores the contents of the registers in the order D0-D7, A0-A6, regardless of the order in the register list.

The MOVEM instruction can also be used to save a set of registers in memory. In addition to the preceding predecrement and postincrement modes for the effective address, the MOVEM instruction allows all the control modes. If the effective address is in one of the control modes, such as absolute short, then the registers are transferred starting at the specified address and up through higher addresses. The order of transfer is from DO to D7 and then from AO to A6. For example, MOVEM. W A5/0l/03/Al-A3, $2000 transfers the low 16-bit contents of Dl, D3, AI, A2, A3, and A5 to locations $2000, $2002, $2004, $2006, $2008, and $200A, respectively.

The MOVEQ. L # $d8, Dn instruction moves the immediate 8-bit data into the low byte of Dn. The 8-bit data is then sign-extended to 32 bits. This is a one-word instruction. For example, MOVEQ. L # $8 F, 05 moves $FFFFFF8F into D5.

To transfer data between the 68000 data registers and 6800 (8-bit) peripherals, the MOVEP instruction can be used. This instruction transfers 2 or 4 bytes of data between a data register and alternate byte locations in memory, starting at the location specified and incrementing by 2. Register indirect with displacement is the only addressing mode used with this instruction. If the address is even, all transfers are made on the high-order half of the data bus; if the address is odd, all transfers are made on the low-order half of the data bus. The high-order byte to/from the register is transferred first, and the low-order byte is transferred last. For example, consider MOVEP. L $0020 (A2), 01. If [A2] = $00002000, [00202016] = 02, [00202216] = 05, [00202416] = 01, and [00202616] = 04, then, after execution of this MOVEP instruction, Dl will contain 02050104 ₁₆•

EXG and SWAP Instructions

The EXG. L Rx, Ry instruction exchanges the 32-bit contents of Rx with that of Ry. The exchange is between two data registers, two address registers, or an address register and a data register. The EXG instruction exchanges only 32-bit-long words. The data size (L) does not have to be specified after the EXG instruction because this instruction has only one data size (L) and it is assumed that the default is this single data size. No flags are affected. The SWAP. W Dn instruction, on the other hand, exchanges the low 16 bits of Dn with the high 16 bits of Dn. All condition codes are affected.

LEA and PEA Instructions

The LEA. L (EA), An instruction moves an effective address (EA) into the specified address register. The (EA) can be calculated based on the addressing mode of the source. For example, LEA $0 0 2 56 0 2 2, A5 moves $002S6022 into AS. This instruction is equivalent to MOVEA. L # $0 02 5 6022, A5. Note that $002S6022 is contained in PC. It should be pointed out that the LEA instruction is very useful when address calculation is desired during program execution. The (EA) in LEA specifies the actual data to be loaded into An, whereas the (EA) in MOVEA specifies the address of actual data. For example, consider LEA $0 4 (A5, D2 .W) , A3. If [AS] = 00002000 16 and [D2] = 0028 16, then the LEA instruction moves 0000202C 16 into A3. On the other hand, MOVEA $04 (A5, 02. W) , A3 moves the contents of 00202C ₁₆ into A3. Therefore, it is obvious that if address calculation is required, the instruction LEA is very useful.

The PEA.L (EA) computes an effective address and then pushes it on to the Supervisor stack (S=l) or User stack (S=O). This instruction can be used when the 16- bit address in absolute short mode is required to be pushed onto the stack. For example, consider PEA.L $9000 in the user mode. If [A7]=$00003006, then $9000 is sign-extended to 32 bits ($FFFF9000). The low-order 16 bits ($9000) are pushed at $003004, and the high order 16 bits ($FFFF) are pushed at $003002.

LINK and UNLK Instructions

Before calling a subroutine, the main program quite often transfers the values of certain parameters to the subroutine. It is convenient to save these variables onto the stack before calling the subroutine. These variables can then be read from the stack and used by the subroutine for computations. The 68000 LINK and UNLK instructions are used for this purpose. In addition, the 68000 LINK instruction allows one to reserve temporary storage for the local variables of a subroutine. This storage can be accessed as needed by the subroutine and can be released using UNLK before returning to the main program. The LINK instruction is usually used at the beginning of a subroutine to allocate stack space for storing local variables and parameters for nested subroutine calls. The UNLK instruction is usually used at the end of a subroutine before the RETURN instruction to release the local area and restore the stack pointer contents so that it points to the return address.

The LINK An, #- displacement instruction causes the current contents of the specified An to be pushed onto the system stack. The updated SP contents are then loaded into An. Finally, a sign-extended twos complement displacement value is added to the SP. No flags are affected. For example, consider LINK A5, #-$10 0. If [AS] = 00002100 16 and [USP] = 00004104 16,then after execution of the LINK instruction, the situation shown in Figure 10.4 occurs. This means that after the LINK instruction, [AS]= $00002100 is pushed onto the stack and the [updated USP] = $004100 is loaded into AS. USP is then loaded with $004000 and therefore 10016 locations are allocated to the subroutine at the beginning of which this particular LINK instruction can be used. Note that AS cannot be used in the subroutine.

The UNLK instruction at the end of this subroutine before the RETURN instruction releases the 10016 locations and restores the contents of AS and USP to those prior to using the LINK instruction. For example, UNLK A5 will load [AS] = $00004100 into USP and the two stack words $00002100 into AS. USP is then incremented by 4 to contain $00004104. Therefore, the contents of AS and USP prior to using the LINK instruction are restored.

In this example, after execution of the LINK, addresses $0003FF and below can be used as the system stack. One hundred (Hex) locations starting at $004000 and above can be reserved for storing the local variables of the subroutine. These variables can then be accessed with an address register such as AS as a base pointer using the address register indirect with displacement mode. MOVE. W d (A5) , Dl for read and MOVE. W Dl, d (A5) for write are typical examples.

The LINK instruction is used in this case to allocate 50 bytes for local variables. At the end of the subroutine, UNLK A2 is used before RTS to restore the original values of the registers and the stack. RTS returns program execution in the main program.

10.6.2 Arithmetic Instructions

These instructions allow:

• 8-, 16-, or 32-bit additions and subtractions.
• 16-bit by 16-bit multiplication (both signed and unsigned) and 32-bit by 16-bit division (both signed and unsigned)
• Compare, clear, and negate instructions.
• Extended arithmetic instruction for performing multiprecision arithmetic.
• Test (TST) instruction for comparing the operand with zero.
• Test and set (TAS) instruction, which can be used for synchronization in a multiprocessor system.

The 68000 arithmetic instructions are summarized in Table 10.6. Let us now explain the arithmetic instructions.

NOTE: If source (EA) in the ADDA or SUBA instruction is an address register, the operand length is WORD or LONG WORD.

(EA) in any instruction is calculated using the addressing mode used.

All instructions except ADDA and SUBA affect condition codes.

• Source (EA) in the above ADD, ADDA, SUB, and SUBA can use all modes. Destination (EA) in the above ADD and SUB instructions can use all modes except An. relative, and immediate.

• Destination (EA) in ADDI and SUBI can use all modes except An. relative, and immediate.

• Destination (EA) in ADDQ and SUBQ can use all modes except relative and immediate.

• (EA) in all multiplication and division instructions can use all modes except An.

• Source (EA) in CMP and CMPA instructions can use all modes.

• Destination (EA) in CMPI can use all modes except An, relative, and immediate.

• (EA) in CLR and NEG can use all modes except An, relative, and immediate.

• (EA) in NEGX can use all modes except An, relative and immediate.

• (EA) in TST can use all modes except An, relative, and immediate.

• (EA) in TAS can use all modes except An, relative, and immediate.

Addition and Subtraction Instructions

• Consider ADD. W $122 0 00, D0. If[122000 16] = 0012 16 and [DO]= 000216, then, after execution of this ADD, the low 16 bits of DO will contain 0014 ₁₆• C = 0 (No Carry), X = 0 (Same as C), V=O (No Overflow since previous Carry and the final Carry are the same), N = 0 (Most Significant Bit of the result is 0), Z = 0 (Nonzero result).

• The ADDI instruction can be used to add immediate data to a register or memory location. The immediate data follows the instruction word. For example, consider ADDI. W #$ 0 012, $1002 00. If [10020016] = 0002 16, then, after execution of this ADDI, memory location 10020016 will contain 001416•

• ADDQ adds a number from 0 to 7 to the register or memory location in the destination operand. This instruction occupies 16 bits, and the immediate data 0 to 7 is specified by 3 bits in the instruction word. For example, consider ADDQ. B #2, Dl. If [D1]1ow byte= 20 16, then, after execution of this ADDQ, the low byte of register Dl will contain 2216·

• All subtraction instructions subtract the source from the destination. For example, consider SUB. W D2, $1222 00. lf[D2]1owworct = 0003 16 and [12220016] = 0007 16, then, after execution of this SUB, memory location 12220016 will contain 000416•

Multiplication and Division Instructions

The 68000 instruction set includes both signed and unsigned multiplication of integer numbers.

Compare, Clear, and Negate Instructions

• The Compare (CMP) instruction subtracts source from destination providing no result of subtraction; all condition codes are affected based on the result. Note that the SUBTRACT instruction provides the result and also affects the Condition Codes. Consider CMP. B D3, DO . If prior to execution of the instruction, [DO.B] = $40 and [D3.B] = $30 then after execution of CMP. B D3, DO, the condition codes are as follows: C = 0, X= 0, Z = 0, N = 0, and V = 0. Suppose it is desired to find the number of matches for an 8-bit number in a 68000 register such as D5.B in a data array (stored from low to high memory) of 50 bytes in memory pointed to by AO. The following instruction sequence with CMP. B (AD)+, D5 rather than SUB. B (AD) +, D5 can be used:

In the above, if SUB. B (AO) +,OS were used instead of CMP. B (AO) +, DS, the number to be matched needs to be loaded after each subtraction because the contents of D5.B would have been lost after each SUB. Since we are only interested in the match rather than the result, CMP. B (AO) +, DS instead of SUB. B (AD)+, DS should be used in the above.

• The 68000 instruction set includes a memory to memory COMPARE instruction. Forexample, CMPM.W (AD)+, (Al)+.If[A0]=00100000 16,[A1]=00200000 16, [ 100000 16] = 0005 1"’ and [20000016] = 0006 16,then, after this CMPM instruction, N = 0, C = 0, X= 0, V = 0, Z = 0, [AO] = 00100002 16,and [AI]= 00200002 ₁₆•

• CLR. L DS clears all32 bits ofD5 to zero.

• Consider NEG. W (AD). If[AO] = 00200000 16 and [200000] = 510, then after this NEG instruction, the low I6 bits of location 200000 16 will contain FFFB ₁₆•

Extended Arithmetic Instructions

• The ADDX and SUBX instruction can be used in performing multiprecision arithmetic because there are no ADDC (add with carry) or SUBC (subtract with borrow) instructions. For example, in order to perform a 64-bit addition, the following two instructions can be used:

Note that in this example, DIDO contain one 64-bit number and D6D5 contain the other 64-bit number. The 64-bit result is stored in D6D5.

• Consider EXT. W D2. If[D2]1owbyte = F3 ₁₆, then, after the EXT, [D2]1owword = FFF3 _16•

• An example of sign extension is that, to multiply a signed 8-bit number by a signed 16-bit number, one must first sign-extend the signed 8-bit into a signed 16-bit number and then the instruction IMUL can be used for 16 x I6 signed multiplication. For unsigned multiplication of a 16-bit number by an 8-bit number, the 8-bit number must be zero extended to I6 bits using logical instruction such as AND before using the MUL instruction.

Test Instruction

Consider TST. W (AO). If [AO] = 00300000 16 and [30000016] = FFFF 16, then, after the TST. W (AD), the operation FFFF 16 – 0000 16 is performed internally by the 68000, Z is cleared to 0, and N is set to 1. The V and C flags are always cleared to 0.

Test and Set Instruction

TAS. B (EA) is usually used to synchronize two processors in multiprocessor data transfers. For example, consider the two 68000-based microcomputers with shared RAM as shown in Figure 10.5.

Suppose that it is desired to transfer the low byte of D0 from processor 1 to the low byte of D2 in processor 2. A memory location, namely, TRDATA, can be used to accomplish this. First, processor 1 can execute the TAS instruction to test the byte in the shared RAM with address TEST for zero value. If it is, processor 1 can be programmed to move the low byte of D0 into location TRDATA in the shared RAM. Processor 2 can then execute an instruction sequence to move the contents of TRDATA from the shared RAM into the low byte ofD2. The following instruction sequence will accomplish this:

Note that in these instruction sequences, TAS. B TEST checks the byte addressed by TEST for zero. If [TEST] = 0, then Z is set to 1; otherwise, Z = 0 and N = 1. After this, bit 7 of [TEST] is set to 1. Note that a zero value of [TEST] indicates that the shared RAM is free for use, and the Z bit indicates this after the TAS is executed. In each of the instruction sequences, after a data transfer using the MOVE instruction, [TEST] is cleared to zero so that the shared RAM is free for use by the other processor. To avoid testing the TEST byte simultaneously by two processors, the TAS is executed in a read-modify-write cycle. This means that once the operand is addressed by the 68000 executing the TAS, the system bus is not available to the other 68000 until the TAS is completed.

MOTOROLA MC68000

This chapter describes the basic features of Motorola’s MC68000 (16-bit microprocessor). The addressing modes, instruction set, I/O, and system design concepts of the MC68000 are covered in detail.

Motorola’s original MC68000 was designed using HMOS technology. Motorola’s MC68000 is replaced it by a lower power MC68HC000, which is designed using HCMOS technology. The MC68HC000 is equivalent to the MC68000 in all aspects except that the MC68HC000 is designed using HCMOS whereas the MC68000 was designed using HMOS technology. This means that unlike the MC68000, the unused inputs of the MC68HC000 should not be kept floating, they should be connected to +5 V, ground, or outputs of other chips as appropriate. Also, note that an HCMOS output can drive l 0 LSTTL inputs. However, an LSTTL output is not guaranteed to provide HCMOS input voltage. Hence, the HCT gates may be required when driving HC inputs. The MC 68HC000 has the same registers, addressing modes, instruction set, pins and signals, and I/O capabilities as the MC68000. The term "MC68000" will be used interchangeably with the term "MC68HC000" throughout this chapter.

The MC68HC000, implemented in HCMOS, is applicable to designs for which the following considerations are relevant:

• The MC68HC000 completely satisfies the input/output drive requirements ofHCMOS logic devices.
• The· MC68HC000 provides an order of magnitude reduction in power dissipation when compared to the HMOS MC68000.
• The minimum operating frequency of the MC68HC000 is 4 MHz.

Although the MC68HC000 is implemented with input protection diodes, care should be exercised to ensure that the maximum input voltage specification (-0.3 V to +6.5 V) is not exceeded.

10.1 Introduction

The MC68000 is Motorola’s first 16-bit microprocessor. Its address and data registers are all 32 bits wide, and its ALU is 16 bits wide. The 68000 requires a single 5-V supply. The processor can be operated from a maximum internal clock frequency of 25 MHz. The 68000 is available in several frequencies, including 4, 6, 8, 10, 12.5, 16.67, and 25 MHz. The 68000 does not have on-chip clock circuitly and therefore, requires an external crystal oscillator or clock generator/driver circuit to generate the clock.

The 68000 has several different versions, which include the 68008, 68010, and 68012. The 68000 and 68010 are packaged either in a 64-pin DIP (dual in-line package)

with all pins assigned or in a 68-pin quad pack or PGA (pin grid array) with some unused pins. The 68000 is also packaged in 68-terminal chip carrier. The 68008 is packed in a 48- pin dual in-line package, whereas the 68012 is packed in an 84-pin grid array. The 68008 provides the basic 68000 capabilities with inexpensive packaging. It has an 8-bit data bus, which facilitates the interfacing of this chip to inexpensive 8-bit peripheral chips. The 680 I 0 provides hardware-based virtual memory support and efficient l00ping instructions. Like the 68000, it has a 16-bit data bus and a 24-bit address bus. The 68012 includes all the 68010 features with a 31-bit address bus. The clock frequencies of the 68008, 68010, and 68012 are the same as those of the 68000. The following table summarizes the basic differences among the 68000 family members:

To implement operating systems and protection features, the 68000 can be operated in two modes: supervisor and user. The supervisor mode is also called the "operating system mode." In this mode, the 68000 can execute all instructions. The 68000 operates in one of these modes based on the S bit of the status register. When the S bit is 1, the 68000 operates in the supervisor mode; when the S bit is 0, the 68000 operates in the user mode.

Table 10.1 lists the basic differences between the 68000 user and supervisor modes. From Table I 0.1, it can be seen that the 68000 executing a program in the supervisor mode can enter the user mode by modifying the S bit of the status register to 0 via an instruction. Instructions such as MOVE to SR, ANDI to SR, and EORI to SR can be used to accomplish this. On the other hand, the 68000 executing a program in the user mode can enter the supervisor mode only via recognition of a trap, reset, or interrupt. Note that, upon hardware reset, the 68000 operates in the supervisor mode and can execute all instructions. An attempt to execute privileged instructions (instructions that can only be execut.ed in the supervisor mode) in the user mode will automatically generate an internal interrupt (trap) by the 68000.

The logical level in the 68000 function code pin (FC2) indicates to the external devices whether the 68000 is currently operating in the user or supervisor mode. The 68000 has three function code pins (FC2, FC1, and FCO), which indicate to the external devices whether the 68000 is accessing supervisor program/data or user program/data or performing an interrupt acknowledge cycle.

The 68000 can operate on five different data types: bits, 4-bit binary-coded decimal (BCD) digits, bytes, 16-bit words, and 32-bit long words. The 68000 instruction set includes 56 basic instruction types. With 14 addressing modes, 56 instructions, and 5 data types, the 68000 contains over I 000 op-codes. The fastest instruction is one that copies the contents of one register into another register. It is executed in 500 ns at an 8- MHz clock rate. The slowest instruction is 32-bit by 16-bit divide, which in executed in 1.25 JlS at 8 MHz. The 68000 has no I/O instructions. Thus, the I/O is memory mapped.

Hence, MOVE instructions between a register and a memory address are also used as I/O instructions. The MC68000 is a general-purpose register-based microprocessor. Although the 68000 PC is 32 bits wide, only the low-order 24 bits are used. Because this is a byte-

addressable machine, it follows that the 68000 microprocessor can directly address 16 MB of memory. Note that symbol [ ] is used in the examples throughout this chapter to indicate the contents of a 68000 register or a memory location.

10.2 68000 Registers

Figure 10.1 shows the 68000 registers. This microprocessor includes eight 32-bit data registers (DO-D7) and nine 32-bit address registers (AO-A 7 plus A 7′). Data registers normally hold data items such as 8-bit bytes, 16-bit words, and 32-bit long words. An address register usually holds the memory address of an operand; AO-A6 can be used as 16- or 32-bit. Because the 68000 uses 24-bit addresses, it discards the uppermost 8 bits (bits 24-31) while using the address registers to hold memory addresses. The 68000 uses A7 or A7′ as the user or supervisor stack pointer (USP or SSP), respectively, depending on the mode of operation.

The 68000 status register is composed of two bytes: a user byte and a system byte (Figure 10.2). The user byte includes typical condition codes such as C, V, N, Z, and X. The meaning of the C, V, N, and Z flags is obvious. Let us explain the meaning of the X bit. Note that the 68000 does not have any ADDC or SUBC instructions; rather, it has ADDX and sUBX instructions.

Because the flags C and X are usually affected in an identical manner, one can use ADDX or SUBX to reflect the carries or borrows in multiprecision arithmetic. The contents of the system byte include a 3-bit interrupt mask (12, II, 10), a supervisor flag (S), and a trace flag (T). When the supervisor flag is 1, then the system operates in the supervisor mode; otherwise, the user mode of operation is assumed. When the trace flag is set to 1, the processor generates a trap (internal interrupt) after executing each instruction. A debugging routine can be written at the interrupt address vector to display registers and/or memory after execution of each instruction. Thus, this will provide a single-stepping facility. Note that the trace flag can be set to one in the supervisor mode by executing the instruction ORI# $8000, SR.

The interrupt mask bits (12, I I, 10) provide the status of the 68000 interrupt pins IPL2, IPLI and IPLO. 12 II 10 = 000 indicates that all interrupts are enabled. 12 II 10 = 111 indicates that all maskable interrupts except the nonrnaskable interrupt (Level 7) are disabled. The other combinations of 12, 11, and 10 provide the maskable interrupt levels. Note that the signals on the IPL2, IPLI and IPL0 pins are inverted internally and then compared with 12, II, and 10, respectively.

10.3 68000 Memory Addressing

The MC68000 supports bytes (8 bits), words (16 bits), and long words (32 bits) as shown in Figure I 0.3. Byte addressing includes both odd and even addresses (0, I, 2, 3, …), word addressing includes only even addresses in increments of 2 (0, 2, 4, …), and long word addressing contains even addresses in increments of 4 (0, 4, 8, …). As an example of 68000 addressing structure, consider MOVE • L D 0 , $50 6 0 8 0 . If [DO] == $07F 12481, then after this MOVE, [$506080] == $07, [$50608I] = $Fl, [$506082] = $24, and [$506083)

= $81. In the 68000, all instructions must be located at even addresses for byte, word, and

long word instructions; otherwise, the 68000 generates an internal interrupt. The size of each 68000 instruction is even multiples of a byte. This means that once the programmer writes a program starting at an even address, all instructions are located at even addresses after assembling the program. For byte instructions, data can be located at even or odd addresses. On the other hand, data for word and long word instruction must be located at even addresses; otherwise the 68000 generates an internal interrupt.

Note that in 68000 for word and long word data, the low-order address stores the high-order byte of a number. This is called Big-endian byte ordering.

10.4 68000 Addressing Modes

The 14 addressing modes of the 68000 shown in Table 10.2 can be divided into 6 basic groups: register direct, address register indirect, absolute, program counter relative, immediate, and implied.

As mentioned, the 68000 has three types of instructions: no operand, single operand, and double operand. The single-operand instructions contain the effective address (EA) in the operand field. The EA for these instructions is calculated by the 68000 using the addressing mode used for this operand. In the case of two-operand instructions, one of the operands usually contains the EA and the other operand is usually a register or memory location. The EA in these instructions is calculated by the 68000 based on the addressing

mode used for the EA.

Some two-operand instructions have the EA in both operands. This means that the operands in these instructions use two addressing modes. Note that the 68000 address registers do not support byte-sized operands. Therefore, when an address register is used as a source operand, either the low-order word or the entire long word operand is used, depending on the operation size. When an address register is used as the destination operand, the entire register is affected regardless of operation size. If the operation size is a word, an address register in the destination operand is sign-extended to 32 bits after the operation is performed. Data registers, on t!1e Jther hand, support data operands of byte, word, or long word size.

To identify the operand size of an instruction, the following notation is placed after a 68000 mnemonic: .B for byte, .W or none (default) for word, and .L for long word. For example,

10.4.1 Register Direct Addressing

In this mode, the eight data registers (DO-D7) or seven address registers (AO-A6) contain the data operand. For example, consider ADD. W $ 0 0 50 0 0, DO. The destination operand of this instruction is in data register direct mode. Now, if [005000] = 000216 and [DO.W] = 000316, then after execution of ADD $005000, DO, the contents ofDO.W = 0002 + 0003 = 0005. Note that in this instruction, the$ symbol is used by Motorola to represent hexadecimal numbers. Also note that instructions are not available for byte operations using address registers.

10.4.2 Address Register Indirect Addressing

There are five different types of address register indirect mode. In this mode, an address register contains the effective address. For example, consider CLR. W (Al). If [Al. L]=$00003000, then, after execution of CLR. W (Al) , the 16-bit contents of memory location $003000 will be cleared to zero.

The postincrement address register indirect mode increments an address register by 1 for byte, 2 for word, and 4 for long word after it is used. For example, consider CLR. L (AO) +. If[AO] = 00005000 16, then after execution ofCLR. L (AO) +,the 16-bit contents of each of the memory locations 005000 16 and 005002 16 are cleared to zero and [AO] = 00005000 + 4 = 00005004. The postincrement mode is typically used with memory arrays stored from LOW to HIGH memory locations. For example, to clear I 00016 words starting at memory location 003000 16 and above, the following instruction sequence can be used:

Note that the symbol# in the above is used by the Motorola assember to indicate the immediate mode. This will be discussed later in this section. Also, note that CLR. W (AO) + automatically points to the next location by incrementing AO by 2 after clearing a memory location.

The predecrement address register indirect mode, on the other hand, decrements an address register by 1 for byte, 2 for word, and 4 for long word before using a register. For example, consider CLR. W – (AO). If [AO] = $00002004, then the content of AO is first decremented by 2-that is, [AO] = 00002002 16. The content of memory location 002002 is then cleared to zero. The predecrement mode is used with arrays stored from HIGH to LOW memory locations. For example, to clear I 00016 words starting at memory location 004000 16 and below, the following instruction sequence can be used:

In this instruction sequence, CLR. w – (A0) first decrements A0 by 2 and then clears the location. Because the starting address is 004000 16, A0 must initially be loaded with 00004002 ₁₆• It should be pointed out that the predecrement and postincrement modes can be combined in a single instruction. A typical example is MOVE. W (AS)+ 1- (A3).

The two other address register modes provide accessing of the tables by allowing offsets and indexes to be included with an indirect address pointer. The address register indirect with offset mode determines the effective address by adding a 16-bit signed integer to the contents of an address register. For example, consider MOVE. W $10 (AS) 1 D3 in which the source operand is in address register indirect with offset mode. If [A5] = 00002000 16 and [002010]16 = 0014 16, then, after execution of MOVE. W $10 (AS), D3, register D3.W will contain 0014₁₆•

The indexed register indirect with offset mode determines the effective address by adding an 8-bit signed integer and the contents of a register (data or address register) to the contents of an address (base) register. This mode is usually used when the offset from the base address register needs to be varied during program execution. The size of the index register can be a signed 16-bit integer or an unsigned 32-bit value. As an example, consider MOVE. W $10 (A4 1 D3. W) 1 D4 in which the source is in the indexed register indirect with offset mode. Note that in this instruction A4 is the base register and D3.W is the 16-bit index register (sign-extended to 32 bits). This register can be specified as 32 bits by using D3 .L in the instruction, and I 016 is the 8-bit offset that is sign-extended to 32 bits. If [A4] = 00003000 16, [D3.W] = 0200 16, and [00321016] = 002416, then this MOVE instruction will load 0024 16 into the low 16 bits of register D4.

The address register indirect with offset mode can be used to access a single table. The offset (maximum 16 bits) can be the starting address of the table (fixed number), and the address register can hold the index number in the table to be accessed. Note that the starting address plus the index number provides the address of the element to be accessed in the table. For example, consider MOVE .W $34 0 0 (AS) 1 D1. If A5 contains 04, then this MOVE instruction transfers the contents of 3404 (i.e. the fifth element, 0 being the first element) into the low 16 bits of D 1. The indexed register indirect with offset mode, on the other hand, can be used to access multiple tables. Here, the offset (maximum 8 bits) can be the element number to be accessed. The address register pointer can be used to hold the starting address of the table containing the lowest starting address, and the index register can be used to hold the difference between the starting address of the table being accessed and the table with the lowest starting address. For example, consider three tables, with table I starting at 002000 16, table 2 at 003000 16, and table 3 at 004000 16. To transfer

the seventh element (0 being the first element) in table 2 to the low 16 bits of register D0,

the instruction MOVE .W $ 0 6 ( A2 , D1.W) 1 D0 can be used, where [A2] = the starting address of the table with the lowest address(= 002000 ₁₆ in this case) and [D How 16 bits =the difference between the starting address of the table being accessed and the starting address of the table with the lowest address= 003000 ₁₆ – 002000 ₁₆ = l 000₁₆• Therefore, this MOVE instruction will transfer the contents of address 003006 16 (the seventh element in table 2) to register DO. The indexed register indirect with offset mode can also be used to access two-dimensional arrays such as matrices.

10.4.3 Absolute Addressing

In this mode, the effective address is part of the instruction. The 68000 has two modes: absolute short addressing, in which a 16-bit address is used (the address is sign-extended to 24 bits before use), and absolute long addressing, in which a 24-bit address is used. For example, consider ADD $2 0 0 0, D2 as an example of the absolute short mode. If [$002000] = 0012₁₆ and [D2.W] = 001016,then, after executing ADD $2 0 0 0, D2, register D2.W will contain 0022₁₆• The absolute long addressing mode is used when the address size is more than 16 bits. For example, MOVE • W $2 4 0 0 0 0 , D 5 loads the 16-bit contents of memory location 240000 16 into the low 16 bits ofD5. The absolute short mode includes an address ADDR in the range of O s ADDR s $7FFF or $FF8000 s ADDR s $FFFFFF. Note that a single instruction may use both short and long absolute modes, depending on whether the source or destination address is less than, equal to, or greater than the 16-bit address. A typical example is MOVE .w $50 0 0 0 2 , $10 0 0. Also, note that the absolute long mode must be used for MOVE to or from address $008000. For example, MOVE. W $8000,D1 will move the 16-bit contents of location $FF8000 to D1 while MOVE. W $008000,D 1 will transfer the 16-bit contents of address $008000 to D 1.

10.4.4 Program Counter Relative Addressing

The 68000 has two program counter relative addressing modes: relative with offset and relative with index and offset. In the relative with offset mode, the effective address is obtained by adding the contents of the current PC with a signed 16-bit displacement. This mode can be used when the displacement needs to be fixed during program execution. Typical branch instructions such as BEQ, BRA, and BLE use the relative with offset mode. This mode can also be used by some other instructions. For example, consider ADD $30 (PC) , D5, in which the source operand is in the relative with offset mode. Now suppose that the current PC contents is $002000, the content of 002030 16 is 0005, and the low 16 bits of D5 contain 0010₁₆• Then, after execution of this ADD instruction, D5 will contain 0015₁₆•

In the relative with index and offset mode, the effective address is obtained by adding the contents of the current PC, a signed 8-bit displacement (sign-extended to 32 bits), and the contents of an index register (address or data register). The size of the index register can be 16 or 32 bits wide. For example, consider ADD. W $4 (PC, DO. W), D2. If [D2] = 00000012 16, [PC]= 002000 16, [D0]10w 16 bits = 001016,and [002014] = 000216, then, after this ADD, [D2]1ow 16 bits= 0014₁₆• This mode is used when the displacement needs to be changed during program execution by modifying the content of the Index register.

An advantage of the relative mode is that the destination address is specified relative to the address of the instruction after the instruction. Since the 68000 instructions with relative mode do not contain an absolute address, the program can be placed anywhere in memory which can still be excuted properly by the 68000. A program which can be placed anywhere in memory, and can still run correctly is called a "relocatable" program. It is a good practice to write relocatable programs.

10.4.5 Immediate Data Addressing

Two immediate modes are available with the 68000: immediate and quick immediate modes. In immediate mode, the operand data is constant data, which is part of the instruction. For example, consider ADDI. w #$0005, D0. If [DO.W] = 0002₁₆, then, after this ADDI instruction, [DO.W] = 0002 ₁₆ + 0005₁₆ = 0007₁₆• Note that the# symbol is used by Motorola to indicate the immediate mode. Quick immediate (ADD or SUBTRACT) mode allows

one to increment or decrement a register or a memory location (.B, .W, .L) by a number from 0 to 7. For example, ADDQ. B #1, D0 increments the low 8-bit contents of D0 by 1. Note that immediate data, 1 is inherent in the instruction. That is, data 0 to 7 is contained in the three bits of the instruction. Note that ADDQ.B #0, Dn is similar to NOP instruction.

10.4.6 Implied Addressing

The instructions using implied addressing mode do not require any operand, and registers such as PC, SP, or SR are referenced in these instructions. For example, RTS returns to the main program from a subroutine by placing the return address into PC using the PC implicitly.

It should be pointed out that in the 68000 the first operand of a two-operand instruction is the source and the second operand is the destination. Recall that in the case of the 8086, the first operand is the destination and the second operand is the source.