In the above discussion of memory interfacing, we focused on certain aspects of the communication process between the Z80 and memory. However, in order to avoid distraction from basic concepts, we did not address several important issues. Now we will attempt to answer those questions briefly or provide references for them : . .
-
How do you determine whether a memory chip is too slow for a given Z80 system?
The response time of a memory chip is defined in terms of Access Time.
This is the time delay between when the microprocessor places a memory address on the address bus and when memory places a data byte on the data bus. Typically, Access Time is 50-450 ns for static RIW memory. Similarly, the microprocessor has a timing specification: the time delay after the Z80 places an address on the address bus to When it begins to read data on the data bus. The memory access time must be less than this microprocessor time delay. This will be dis. cussed when we consider advanced topics in memory interfacing .
2 . How do you interface a memory chip with slow response time?
If the memory response time is slower than the microprocessor read time, the Memory Read cycle can be extended by using the WAIT signal. During the T, state of the Memory Read cycle, the Z80 samples the WAIT signal, and if it is row, the Z80 adds Wait states until the signal goes high again. Typically, one Wait state (one clock cycle) provides sufficient time for memory to place data on the data bus. Extra circuitry is necessary for adding Wait states; this is discussed in topic 16.
3. Why did you omit an illustrative example of dynamic memory?
The dynamic memory stores information as a capacitive charge; therefore, information needs to be refreshed every few milliseconds. In the latter part of the Opcode Fetch cycle, the Z80 uses the low-order bus for refresh addresses. To interface the dynamic memory, additional refresh circuits that can use the refresh addresses from the Opcode Fetch cycle are necessary. This will also be discussed in topic 16.