The Essential Guide to Semiconductors – Essential Guide to Custom and Configurable Chips

Essential Guide to Custom and Configurable Chips

In this chapter…

  • Overview of Custom Chips

  • Field-Programmable Chips

  • Custom ASIC Chips

  • Dynamically Reconfigurable Chips

  • Intellectual Property Licensing

  • Future Outlook for Custom Chips

Overview of Custom Chips

Over time, it has become possible for almost anyone to create his or her own custom chip. Instead of being limited to just multinational corporations with billions of dollars invested in manufacturing equipment, chip design is now within reach of the average college student or well-equipped home hobbyist.

These new dilettantes can’t manufacture their own chips, of course. That still does require billion-dollar chip-fabrication factories. However, it is possible to design your own chip. To make it real, you can either have a big company manufacture it for you, or you can “burn” the design into a blank chip made for the purpose. Either way, it’s an opportunity for the budding chip designer to see his or her creation in silicon.

Of course, there are trade-offs, and the trade-offs here have to do with cost, performance, and quantity. The more you’re willing to spend, the faster your chips can go. The very fastest custom chips cost nearly $1 million to make, so they’re obviously limited to serious customers only; home-brew hackers need not apply. However, if you’re willing to sacrifice a little top-end performance, it’s entirely possible to make one custom chip for about $100. Even serious companies often make dozens or thousands of prototype chips using low-cost means before committing big money to a high-end chip.

In this chapter, we review the half-dozen options available for making custom chips. We look at the cost, performance, and volume trade-offs required and take a peek into the future of custom chips.


About Custom Chips

Custom and customizable chips come in a lot of different types and categories. For our purposes, we can divide them into three classes. First, we look at field-programmable chips. These are the lowest cost, and lowest performance, option. Next, there are “hard” custom chips that offer maximum performance for high-volume customers willing to pay the considerable price. Finally, there is a new third class of dynamically reconfigurable chips that are just starting to make a mark on the market. If their promoters’ claims are true, dynamically reconfigurable chips could be the wave of the future.

Field-Programmable Chips

Our first category of customizable chips are called field-programmable chips because they are programmed “in the field,” meaning in the customer’s office or laboratory. They could be programmed literally out in a field, but that wasn’t on anyone’s mind when these chips were being developed. Field-programmable chips are like blank slates on which customers can draw their own chip design. Like blackboard slates, these chips are erasable and can be reused for many different chip designs.

The category of field-programmable chips includes some specific types that are called by different names by their manufacturers. Some are called FPGAs, short for field-programmable gate arrays. (A gate array is a technical term for an earlier kind of custom chip, which is covered later in this chapter.) You might also hear them called LCAs, for logic-cell arrays, PALs, for programmed array of logic, or CPLDs, for complex programmable-logic devices. By and large, all these terms refer to the same general thing. Naturally, there are minor differences between the FPGAs from one company and the CPLDs from another, but they share more similarities than differences.

Field-programmable chips aren’t really custom at all. They’re mass-produced like any chip, but customers can customize them after they receive them. Like an Etch-a-Sketch, they’re sold by the millions to happy customers all around the world. Each customer can then use it to create, erase, and re-create nearly any chip design he or she can imagine. With an Etch-a-Sketch, you’re limited only by the size of the screen. With field-programmable chips, you’re limited by the amount of silicon on the chip. Bigger field-programmable chips can hold bigger and more ambitious chip designs, but they also cost more money.

How can a mass-produced chip work like a custom user-designed chip? Field-programmable chips like FPGAs and CPLDs work by dicing up their internal functions and connecting them back together with microscopic fuses or switches. Blowing one fuse disconnects one tiny portion of the chip; leaving the fuse intact leaves that function connected. By carefully deciding which pieces to connect, and how, you can create virtually any electronic design at all.

The whole process is, strangely, a bit like needlepoint. The canvas backing for needlepoint supplies a regular grid pattern, and you essentially connect the dots using colored thread. One little x at a time, a picture slowly starts to emerge. In the same way, field-programmable chips provide a silicon canvas on which you can paint your chip design.

Pushing the analogy a bit further, field-programmable chips waste a lot of silicon the way needlepoint wastes a lot of colored thread on the back of the canvas. This makes FPGAs and similar chips more expensive than usual. It also means field-programmable chips consume more energy than other chips of the same size. Every part of an FPGA that’s disconnected by a blown fuse is a part of the chip that’s wasted because it’s silicon that had to be manufactured, tested, and sold, but is never used by the customer. The ratio of used silicon to unused silicon (called the utilization ratio) thus becomes a big issue for customers who don’t like paying for any more silicon than they have to. Typical utilization ratios for a big FPGA are about 35 percent to 50 percent. You’re extraordinarily lucky if you actually use 75 percent of an FPGA.


Tech Talk

Technically, some FPGAs and CPLDs don’t use fuses; they use antifuses. An antifuse works in the opposite way from a normal fuse, meaning that when you “blow the fuse” you’re actually making a connection, not breaking one. Antifuses have some subtle technical advantages over fuses, and one big disadvantage. They use slightly less electricity, and because most of the fuses (or antifuses) in an FPGA are not connected, you don’t have to blow as many antifuses to get the connection pattern you want. The big downside to antifuses is they can’t be “healed” once they’re blown, so the chip can’t be erased or reprogrammed.

CPLDs tend to be smaller and less expensive than FPGAs. A small CPLD might have a few thousand transistors, cost about $15, and be about the size of a jellybean. A big FPGA will have several million transistors, cost more than $1,000 per chip, and be as big as a box of matches. Both types—and plenty of sizes in between—are very popular and sell by the millions.

Regardless of type, almost all field-programmable chips are erasable and reusable. In other words, you can “heal” their internal fuses to reset the chip to its original blank condition. This is a great boon to chip developers, who can experiment with different designs without fear of throwing $500 chips into the trash every couple of hours. Field-programmable logic is one of the best things to ever happen to young engineers-in-training.

Apart from their comparatively high cost through wasted silicon, field-programmable chips are also slow. It takes time (albeit, very little time) for electricity to pass through the patchwork of fuses that makes up a large FPGA. All that time adds up, so field-programmable chips are much slower than “real” ASIC chips designed and built from the ground up to perform the same function.

You might think this would make FPGAs useful only for small prototype runs or for experimentation. In reality, companies buy FPGAs by the thousands and include them in their own products. Even though these companies know they’re paying a price and performance penalty for using field-programmable logic, it’s still cheaper and easier than manufacturing their own chip. Unless you’ve got a million dollars to spend on development, field-programmable chips are your best alternative.

The field-programmable chip suppliers know this, and their business models rely on customer dependency and addiction. The story is always the same: A new customer buys one or two of the latest expensive FPGA chips thinking they’ll use them just for development or a few experiments. Then they buy a few more for their other engineers. Before long, they’re buying dozens for use in prototypes. When their product is finished, they need still more FPGAs to build the first production run, and down the slippery slope they go. It’s too late to redesign the product around some other type of chip. Time to market is too precious to jettison the FPGAs (which work) and start over with a cheaper alternative (which might not work). After two or three years of this, the customer has consumed thousands of expensive FPGAs and wonders how this compulsion began.

Custom ASIC Chips

For companies with the financial and technical wherewithal, an ASIC is the product of choice. These are “real” custom chips, manufactured using the best process technology to deliver the best performance and lowest power consumption. ASICs aren’t generic like field-programmable chips, although they are mass-produced, but only for one customer. An ASIC is the best opportunity for a moderately funded company to design, own, and sell its own chips.

In this chapter, we use ASIC as a catch-all term for a group of subtly different products and processes that all solve the same problem. ASIC stands for application-specific integrated circuit, which is meant to suggest that the chip is designed for one specific application or product. That’s usually the case, although it’s not a requirement. This group also includes products like ASSP (application-specific standard product) and SoC (system on a chip) devices. The differences among these terms are minor, and are covered shortly, but for now we call them all ASICs.


To ASIC or Not To ASIC

The decision whether or not to make an ASIC comes down to cost: Will you realize a good return on your investment? ASIC development is very expensive, so it’s a project that’s never undertaken lightly, but the benefits can be great: You get exactly the chip you want, in high volume, and all to yourself. You never have to share your ASIC chip with your competitors. Some of today’s most popular products, such as cell phones and laptop computers, wouldn’t be possible without custom ASICs.

However, the cost of developing an ASIC can make strong managers tremble. As a rough estimate, plan on spending $1 million before the first chip is ready. That’s a big investment before you even know for sure if the chip will work. If not, you have to decide whether to pour more time and money into fixing it and making a revised chip. If it does work, you get to decide how much additional money to pour into mass-producing them.

The cost equation for ASICs is a bit schizophrenic. Almost all the cost is up front, tied up in development. After that initial investment, the unit cost of production is relatively cheap. The more chips you make, the more you can amortize the up-front costs across multiple units. Thus, the key to rationalizing an ASIC project is guaranteeing volume production. As a rough rule of thumb, most companies would not consider an ASIC unless volumes were forecast to exceed 50,000 units. At around 250,000 units an ASIC is probably a safe bet, and if you can sell 1 million units, it’s a sure thing.

The costs for an ASIC are exactly the opposite as for an FPGA or other field-programmable chip. FPGAs have no up-front development costs at all, but their unit price is comparatively high. ASICs have very high up-front costs but low unit prices (disregarding amortization). A good business manager would then look at the volume cross-over point to see whether an ASIC or an FPGA makes financial sense. That cross-over changes, of course, for every customer, market, and chip type. Plenty of companies have made the wrong decision, buying FPGAs long after they could have amortized an ASIC, or developing an ASIC when the volumes can’t support it. ASIC development is a prestige job among engineers and a mark of respect among electronics companies, so there’s often some subtle pressure from within the ranks to create an ASIC even if the numbers can’t strictly justify it.


Designing an ASIC

ASICs are designed like any other type of complex chip, using the tools and techniques described in Chapter 3, “How Chips Are Designed.” A team of engineers will work for several months plotting out how the chip will work, then moving on to the detailed design. A number of these engineers will be tasked with double-checking and verifying that everything their colleagues do is correct. The team can’t afford to design a bad chip, and waiting until the first one is built to test it is too risky. ASIC teams need to assure themselves that every transistor, resistor, and capacitor in their chip is exactly where it should be before they commit their creation to silicon.

Once the ASIC design is finished, the engineers will tape out their chip. Today, this is largely a ceremonial event, but it used to be a big deal. The tape of a new chip design is the final design plan, like the blueprints for a new skyscraper. It’s not really a tape any more, and creating the final plans involves pushing a button, but it’s still an emotional milestone for the entire design team. Many of the engineers might receive bonus pay if they tape out ahead of schedule.

Between the time they tape out and the time the first chip arrives from the foundry—a period of several weeks—the engineers bite their nails. There’s nothing more they can do on their million-dollar project except wait and wonder if it will work.


Full-Custom Designs

A full-custom ASIC design is just what it sounds like: a completely custom chip designed by, and built for, one company. This is easily the most expensive way to make a custom chip, but it’s also the most flexible and the only way to achieve the very highest levels of performance. Full-custom ASICs used to be rare but the tools, talents, and technology have all improved to the point where medium-sized electronics companies can create an ASIC every few years. Full-custom ASICs are still not the most common method of making custom chips but they’re the path for top-notch performance.


Standard Cell Designs

Ideally, the ASIC design engineers would have free rein to design anything they want. Realistically, however, there might be cost and time limits on what they can do. It’s also likely that some chip, somewhere, is at least a little bit similar to what the design team envisions. To save time and money, and to take advantage of existing technology, they can create a “standard cell” design. A standard-cell ASIC sacrifices a little flexibility in return for easier development and lower costs.

Standard-cell chips are a bit like FPGAs in that the custom chip is implemented using an array of already existing functions, like a mosaic made of silicon tiles, called standard cells. It’s a modular approach, although a fine-grained one. Standard-cell chips are cheaper than full-custom ASICs because they can be manufactured using semistandard silicon wafers that are partially completed. These require only a little customization during manufacturing, so they’re cheaper to produce. They’re also far easier and less risky to design because the engineers are not creating everything from scratch. Standard-cell ASICs offer a compromise between ultimate flexibility and moderate cost, and most ASICs are now designed using this method.


Gate Array Designs

Gate array ASICs are another alternative to full-custom or standard-cell ASIC design. Like standard cells, gate array chips trade flexibility for simpler manufacturing and lower cost. Gate arrays are not as finely grained as standard cells, which makes them less flexible. Designing a gate array ASIC is like designing with Lego blocks: They can be connected in innumerable different ways, but the result is always a bit blocky.

Like standard cells, gate array ASICs are built using partially completed silicon wafers that are customized late in the manufacturing process. Chips designed using gate array techniques are a bit bigger in silicon area than standard-cell ASICs (and a lot bigger than full-custom chips), which makes them more expensive to manufacture.


Building an ASIC

Third-party semiconductor factories called foundries manufacture the ASIC chips. Foundries are in the business of providing their manufacturing services to any and all comers. Any customer designing an ASIC can pay for the services of a foundry. The foundry business is competitive, and foundries compete on price, availability, delivery time, performance, and all the other things that make a spirited and healthy market. Some foundries specialize in low-cost manufacturing (although your chips might not be the fastest), whereas others have a reputation for leading-edge technology (although you might have to wait in line and pay premium prices).

ASIC design teams generally have to choose their foundry partner midway through the design process. Some of the chip’s design details will depend on who manufactures the chip, and where. These details have to be pinned down before the design is finished.

After the design team tapes out, they send the “tape” (really a big e-mail or a CD-ROM) to the foundry. The foundry might start manufacturing the chip right away, or it might wait until another customer’s chips are finished. You might have to wait for weeks, or even months if business is good, before your chip gets to the front of the production queue. After that, it’s a matter of a few weeks before the finished chips come out the other end of the production line.

Foundries produce large-volume orders all at once to minimize the down time of their expensive equipment. Smaller orders sometimes have to wait behind larger (and presumably, more lucrative) ones. Very small orders of a few hundred chips will be produced on a shuttle run, which is a collection of different customers’ chips processed together on one batch of silicon wafers. Shuttle runs are a compromise for both the customer and the foundry. All the various chips must obviously be compatible with exactly the same production process, because they’ll all be processed at once. This means no mixing fast chips with slow chips. Foundries don’t like shuttle runs because they’re labor intensive and don’t produce much revenue, but they’re the only way to service small customers, and small customers might one day become big customers.

Each ASIC chip will be marked with your own company’s logo, not the foundry’s. Foundries are silent partners in ASIC development, and they like to preserve their customers’ anonymity as well as their own. There’s no easy way to tell what foundry manufactured a particular chip or, in fact, whether it was made at a foundry at all.

Once the chips are ready, they’re shipped back to the customer who designed them. This is an exciting day for the ASIC design team and a nervous one for their managers. In Silicon Valley, this event frequently falls around early springtime, because ASIC teams often cram to finish their design before end-of-year deadlines.

Testing the very first chip is sometimes called the smoke test, to see if the chip smokes. Black smoke or white smoke, it’s all bad. The wry humor among engineers would have us believe that all silicon chips really run on smoke, not electricity. If you let the smoke out of a chip, it stops working, so obviously, it must be smoke-powered.

Dynamically Reconfigurable Chips

A new kind of custom chip has recently become available. The technology is still a little experimental and some of the initial claims seem a bit wild, but if these dynamically configurable chips live up to even some of their promise, they might become a big part of the overall microprocessor and custom-chip businesses.

The concept is called dynamically reconfigurable logic, although it’s known by many other names as well: Reconfigurable computing, adaptive logic, and self-adaptive processing are all terms that are bandied about. Whatever you call it, the idea is certainly interesting.


About Dynamically Reconfigurable Logic

One thing all ASICs have in common is that once the chip is built, it can never be changed. Because it takes nearly a year to design an ASIC, that’s a difficult forecasting job for somebody. Technology can change, markets can change, and competitors can do shifty things in that time. However, all chip makers face the same problem. Making chips is no different from making cars: Once the product rolls off the assembly line, it’s done.

Field-programmable chips alter that equation, allowing engineers (or even sophisticated customers) to reprogram the chips after they’ve shipped. FPGAs were thus supposed to herald a new era of fluid logic, chips that change over time to meet changing conditions. With few exceptions, though, that doesn’t happen. Chip designers almost never redesign an FPGA once it’s out the door and in the customer’s hands. All those field-programmable chips might just as well be fixed silicon.

Dynamically reconfigurable logic aims to change all that. These are chips designed from the outset to change, and change frequently. It takes about a minute to erase a big FPGA and reprogram it, but dynamically reconfigurable chips can change in almost no time at all. Thousands or millions of times each second, these chips can change their stripes, becoming different chips at different times.

The idea is certainly tempting. A dynamically reconfigurable chip could act as a kind of universal logic chip, performing whatever task is required. One moment it’s a microprocessor, the next moment it’s a network chip, and after that it’s a graphics accelerator. The companies making these chips have names like Chameleon and Quicksilver that emphasize their mutability. At the extreme, products could be designed with nothing but one big chip in the middle. Dynamically reconfigurable chips could be cheaper than almost every other kind of chip because one dynamic chip could replace dozens of different old-fashioned, fixed-function chips.

At least that’s the theory. The reality appears to be creeping toward that point, but the hurdles are still significant. For starters, customers are having a hard time grasping the concept. It’s so outlandish that newcomers have a hard time imagining how these chips might be used. It also requires engineers to design multiple different chips and share them in a single physical package, something no one currently is trained to do. If the dynamic chip is also a processor, which it often is, how do you program it? New programs and programming tools have to be devised to deal with a processor that changes its instruction set, registers, buses, and resources moment by moment.

Finally, it threatens the status quo. Engineers are like members of any other profession, so they tend to protect their skills and defend their hard-fought experience. Something entirely new upsets the apple cart, turning all the engineers on a team into inexperienced beginners. Those with the most experience will naturally also be in the position of most authority and put up the most resistance.

Intellectual Property Licensing

ASICs and field-programmable chips are closely tied with another concept called intellectual property. Semiconductor intellectual property (IP) is simply the idea of reusing existing chip designs in new chip designs. Like magpies, chip designers like to borrow and reuse what they can from earlier chips rather than designing every single function of a new chip entirely from scratch. Actually, it’s not even a question of preference anymore; there’s simply no time to design a chip completely from scratch.

An architect designing a skyscraper would no sooner design individual bricks and plumbing fixtures than an engineer would design each transistor or logic gate. It’s only sensible to use preexisting fixtures. Like an architect, a chip designer might want to reuse large pieces from some previous design—an entire microprocessor, perhaps, or a few thousand transistors from a particularly efficient communications chip. This concept is called design reuse among engineers, and the business of supplying reusable functions and features—the plumbing fixtures for silicon skyscrapers—is called intellectual property licensing.

There are several companies that do nothing but create and sell these silicon functions. They create partial chip designs that are meant to be included in larger projects, like designing windows for office buildings. Unlike the window makers, these semiconductor IP companies don’t deliver any physical or tangible product. They merely share their design blueprints under license. Like architects, IP companies are in the business of selling what they know, not what they make.

The IP business model has been compared somewhat uncharitably to the world’s oldest profession. Both are service industries with no cost of goods, low overhead, no inventory, and the same services that are sold to one customer can be sold again to another. Prices are set by market conditions and the merchandise does not age gracefully. In busy times the business is very profitable. It may be labor-intensive, but the margins are good.

Those in a more benevolent frame of mind compare IP licensing to retail franchises. Retail stores and chain restaurants aren’t usually owned by the parent company; they’re franchised to licensed operators who follow an established corporate recipe in return for a share of the revenue. Closer to the technology front, Dolby Laboratories licenses its noise-reduction technology to makers of cassette tape players and Adobe’s PostScript technology appears in most laser printers. Neither company manufactures anything, yet their brand name and technology—their IP—make someone else’s products more valuable.

Among ASIC and FPGA designers, IP is a necessity. It’s impossible to design a 10-million-transistor chip from scratch in a reasonable amount of time. It’s also impossible to verify that the entire thing works unless major portions of the chip have been tried, tested, and guaranteed by someone else beforehand. The bigger and more complex the ASIC design, the greater the need for outside IP.

The most valuable type of semiconductor IP today is microprocessors. Few ASIC designers want, or need, to design their own CPU. Besides, choosing an existing microprocessor makes the ASIC compatible with that microprocessor’s software. A new in-house microprocessor would have no industry support at all, but a popular microprocessor licensed from a major vendor might come with piles of software behind it. Nearly half of all the 32-bit microprocessor chips sold in 2001 were based on licensed designs.


IP Licensing Business

The demand for semiconductor IP is great, but selling IP can be an uphill battle. You’re selling to fellow engineers, and engineers have a tendency to believe that anything you can do, they can do better. This is known as the Not Invented Here (NIH) syndrome. Anything that was not invented here is assumed to be inferior, and the NIH syndrome runs high among chip designers who might have, well, a chip on their shoulders.

At the end of the day, IP really provides your customer with two things: the chance to save time and the chance to blame somebody else. Your customer’s engineering team probably could duplicate your IP given enough time, but why should they? Using outside IP alleviates the burden of designing every part of a new chip from scratch. Second, outside IP doesn’t need to be tested as meticulously as new parts of the chip do. That in itself can save lots of time. If something doesn’t work, the ASIC design team can always blame the outside IP supplier.

Making a profit in the semiconductor IP business takes a long time, if it ever happens. It’s tempting to want to sell a few IP licenses and then relax on the beach until the royalties pour in while dutiful attendants bring tall drinks and wave palm fronds. Sadly, the IP money train takes a long time to build up steam and get rolling.

Creating semiconductor IP is like making movies: It’s all sunk cost before you can sell the first ticket. The designs have to be complete and tested before they can be licensed to others. Once a customer signs a license and you deliver the goods, you’ll wait more than a year before the first royalty check arrives. During that time every IP company needs to survive on its cash in the bank. First comes the breathtaking investment, then comes the long wait for revenue.


IP Revenue Streams

IP companies get their revenue from two or three sources, namely the license fee, royalties, and maintenance payments (see Figure 8.1). Almost all IP suppliers charge an up-front license fee and royalties. The regular maintenance payments might be optional.

Figure 8.1. Most IP payment schedules involve an initial license fee followed by eventual royalties. Regular maintenance payments might al

As the figure shows, the commercial relationship starts with the initial license fee. This is shown as a lump sum, although it is sometimes paid in installments and sometimes after certain development milestones are achieved.

After the license fee comes the royalties, maybe. Royalties aren’t due until the customer produces chips, which might never happen. Designing an ASIC and putting it into production takes 12 to 18 months, so this is the soonest an IP company could expect to see royalties. It’s possible the IP vendor might never receive any royalties at all if the customer’s ASIC project is canceled, the company is acquired, or the chip just doesn’t work. Lots of IP companies make the grim assumption that half of their customers will never pay them any royalties whatsoever.

Royalties can be calculated in a lot of different ways. Some IP companies charge their licensees a flat rate per chip, some charge based on chip price or volume, and some charge over time. Naturally, vendor and customer rarely agree on the most equitable terms, at least at first. IP vendors like to charge high up-front license fees (because so many chips never produce royalties), yet still reap the benefits of the occasional million-seller. Licensees generally prefer royalties that taper off over time or volume, taking advantage of economies of scale and the ever-decreasing cost of production. Licensees frequently agitate for royalty caps after a certain volume or royalty limit, something IP companies never agree to.

Finally, some IP firms charge customers a monthly maintenance or support fee, which generally entitles them to free upgrades to the IP they’ve licensed. Customers might also get preferential treatment for hotline technical support.


IP Summary

IP has become the grease lubricating the gears of chip design. The free exchange of designs (free in the sense of liberte, not gratis) has enabled a new class of business for IP suppliers and for small chip companies that can now consider designing their own chips. It doesn’t require an enormous team of hardware engineers trained in every discipline of manufacturing, design, and testing to create a new chip. Startup companies can license most of the basic subcomponents of their “dream chip” and create the rest themselves. They can concentrate on adding value through original invention, not on redesigning semiconductor wheels.

To the ASIC design teams, IP is more of a time-saver than an important technology, per se. Very little semiconductor IP is so unique or innovative that it couldn’t be duplicated. However, the hurry-up pace of electronics doesn’t tolerate wasted effort. If two-thirds of a chip design can be bought ready-made, then two-thirds of its development time can be slashed from the schedule. Outside IP also provides the not inconsiderable benefit of support. Anything licensed from the outside is presumed to work and is someone else’s problem. The responsibility for anything designed in-house remains squarely in-house.

We’ve already passed the point where it’s impossible to design an entire chip alone (at least, an economically interesting chip). Even a team of engineers working together can’t design a 50-million-transistor chip from scratch and finish it soon enough to be worth the effort. They need to reuse part of the design, even if it’s their own material they’re reusing. As transistor counts increase, so does the need to reuse or purchase larger and larger blocks of IP. Large chips are becoming like patchwork quilts, with pieces snipped and cut and borrowed from various sources. Even though some of the pieces might be old, the quilt is still original.

Future Outlook for Custom Chips

The genie is out of the bottle. Once it became possible to create custom chips, there was no going back. Now the ASIC business generates tens of billions of dollars per year, a significant part of the overall semiconductor economy. Just as important, custom and customizable chips have enabled new kinds of products, and allowed products to get to market faster. Custom chips complement the mass-market chips produced by big chip companies the way tailored outfits complement off-the-rack clothes.

Yet for all the rising popularity of custom ASICs, some hurdles are fast approaching. Ironically, the very advances in technology that allowed custom chips to exist are now pricing them out of reach. Before, it was technologically impossible to make custom chips; now it’s just unaffordable.

New foundries cost more than $1 billion to construct, and many millions more to upgrade and refit every few years. This puts an enormous burden on every foundry to run at maximum capacity and to produce only the most profitable chips. The economics of chip production are such that overhead costs are huge but incremental costs are negligible. Therefore, volume is key, and that works against ASIC customers.

ASIC customers are like boutique shoppers, but they don’t want to pay boutique prices. A high-volume ASIC (e.g., 1 million units) can easily pay for itself, making both the ASIC customer and its foundry partner happy. However, as volumes decrease to more reasonable and achievable levels, the financial picture darkens. The overhead burden is amortized across fewer chips, making each one more expensive. Worse, foundry operators don’t like to change their tooling for small production runs, making small customers that much less attractive. Yet foundries need volume, so they can’t afford to turn too many customers away.

The situation worsens with every new generation of semiconductor technology. Not only do the foundries and their exotic equipment get even more expensive, the chips they produce get smaller and faster. Faster is okay—everybody likes that; but making chips smaller can be counterproductive. Small chips mean more chips per wafer, so fewer wafers are needed to satisfy a customer’s entire production requirement. Five or 10 wafers can produce tens of thousands of working chips, which might be all the customer needs for a year. Yet that small number of wafers is hardly worth the effort for a foundry operator. It’s hard for their automated systems to track such a small order and it’s awkward to reset the tooling so frequently. However, this appears to be the wave of the future. We’ve gotten too good at manufacturing leading-edge chips. We can produce so many of them at once that anything less than about half a million pieces seems hardly worth the effort. So we come full circle: ASIC design is relegated to the rich and famous, with smaller companies priced out of the market, forced to make do with off-the-rack chips.

All of this is good news, however, if you sell field-programmable chips. Your chips are mass-produced, so volumes are high and production is smooth. There’s no customization, retooling, or tracking required for each customer, either. They do all that on their own. All you have to do is keep producing FPGAs and CPLDs that your customers can use to realize their dreams of a (semi-) custom chip.

A few of the larger FPGA vendors have also started offering IP that’s tailored to their particular brand of field-programmable chips. This is a parallel effort with the commercial IP vendors, who focus almost entirely on full-custom. ASIC customers (because the volumes are higher and the license fees are easier to justify). FPGA-specific IP naturally helps customers design more complex FPGA-based products in less time. Not incidentally, it also ties the customer to a particular FPGA vendor, as one vendor’s IP won’t work with a rival vendor’s FPGA chips. This represents a sound marketing strategy.

FPGA-specific IP doesn’t generate royalties, however. It usually doesn’t bring in licensing revenue, either. Customers are already frustrated by the comparatively high cost of FPGA chips; they’d balk even more if they had to pay royalties on top of that, and the whole point of using field-programmable chips is to avoid the sky-high cost of designing an ASIC, so up-front license fees are also greeted with grim looks.

As field-programmable chips like FPGAs and CPLDs get faster and more capable, and as the costs associated with ASICs continue to increase, more customers will flock to the field-programmable alternative. It’s a compromise between mass-produced volume economics and customer-specificity, but that’s a trade-off many companies are willing to make, as if they had a choice. Slowly, these traditional field-programmable vendors might start to adopt some features from the dynamically reconfigurable proponents, moving this interesting technology into the mainstream.


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