Synchronous demodulator
The rectifier is in essence a switch which closes during one half-cycle of the carrier wave and opens during the other half. From this point of view, any switching device may be used, provided it allows the carrier through for one half-cycle only. Since we are only interested in the amplitude of the peak of the carrier, the switch need only be open for the duration immediately before and immediately after the positive (or negative) peak of the carrier. In truth, the modulated carrier is sampled once every cycle of the carrier, a sampling rate equal to the carrier frequency itself. This is the principle of the synchronous demodulator.
The sampling pulses are obtained by the use of a limiter which removes the envelope and leaves a clipped 39.5 MHz carrier only as shown in Figure 13.12. The switching or sampling pulses, which have the same fre- quency and the same phase as the IF, are used to control a sampling gate that switches on at the peaks of the modulated carrier. The peak levels are then used to charge a capacitor which, given the correct time constant, will reproduce the original modulating signal. An important characteristic of the synchronous demodulator is that it will only demodulate those a.m. waveforms which have a carrier that is equal in frequency to and is in phase with the sampling pulses. In this way, synchronous demodulators remove both stray modulation caused by noise and beat frequencies between the sound IF on one hand and the adjacent vision carrier and adjacent sound inter-carrier on the other.
The output of the synchronous demodulator may be improved by dou- bling the sampling rate. Two switching square waves in antiphase to each other are used to operate two separate gates. The two gates are also fed
with out-of-phase IF signals. The effect is to produce a signal which appears to have passed through a full-wave rectifier. The output contains a carrier component which is twice the frequency of the original carrier, mak- ing it easy to filter out. Synchronous demodulators are too complex and expensive for construction from discrete components but lend them easily to design on a silicon chip as part of an IF or video integrated circuit.
Tuner IC package
An IC package incorporating a tuner, IF stage and vision detector is shown in block-diagram form in Figure 13.13. It uses no conventional tuned circuits and thus needs no tuning control voltage: all its tuning instructions come from the TV’s control microcomputer via the SDA and SCL lines of the I2C control.
This IC tunes from 50 to 860 MHz and uses a double-superhet tech- nique. The RF amplifier stage consists of a wideband gain-controlled low- noise amplifier suitable for use with both aerial and cable input signals. It feeds mixer 1 where the first frequency conversion takes place; in fact it is an up-conversion to a first IF frequency well above 1 GHz. This passes through an external filter, a simple inexpensive two-pole ceramic reso- nator with a bandwidth of about 15 MHz: this defines the initial pass- band and provides image-frequency rejection. In conjunction with on-chip
image-rejecting mixer design, image-signal suppression of 65 dB is achieved over the entire tuning range. The signal then undergoes a sec- ond, down-conversion in mixer 2, whose local oscillator 2 runs at a fre- quency such that the second IF frequency is 39.5 MHz (vision). The second mixer stage is again a special image-rejecting type to provide suppression of 65 dB to the image signal produced in the first mixer stage. The two local oscillators are fully integrated into the IC, and generate the required fre- quencies with reference to a single external crystal. Tuning resolution is 62.5 kHz, giving 128 steps in the (typical) 8 MHz channel width. The system uses a complex frequency-synthesis circuit whose components – varicap diodes, voltage-controlled oscillators, phase/frequency detectors, programmable dividers and charge pumps – are all on the chip. The IF amplifier is gain-controlled in the same way as for a conventional tuner/IF ensemble to optimise the noise performance and minimise cross-modulation when large input signals are present. This device has an a.g.c. range of 96 dB, a noise figure of 8 dB, image rejection of more than 57 dB, and cross- modulation performance of less than 1 dB in the presence of 30 mV input signal.
The ‘tuner-only’ version of the IC in Figure 13.13 ends at the dotted line to the left of diagram centre. The ‘complete-receiver’ IC incorporates further procession which will now be described; either chip can be used for digital TV by taking the IF output signal (top centre) to a suitable demodulator.
Continuing to the right, the 39.5 MHz IF signal is ‘shaped’ in a SAW fil- ter for passage to a further IF amplifier, after which analogue demodula- tion takes place. This involves a PLL locked to the vision carrier frequency. The demodulated video signal passes through an external trap (right of diagram) to take out the sound carrier, then back through a chip-internal noise clipper to remove impulse interference.
Down-converted inter-carrier sound has an FM carrier frequency of 6 MHz for the UK, and is fed through a chroma trap to remove colour sub- carriers, then an on-chip self-tuned filter on its way to the FM demodula- tor. After filtering and de-emphasis, the baseband signal is ready for amplification and passage to the speaker(s). Take-off of a Nicam stereo signal feed is also possible with this IC. The tuner chip is controlled by the industry-standard I2C serial control bus which allows interrogation and readout of the contents of all the status registers on the chip, and enables the device to be programmed in software. Data registers in the tuning PLLs are loaded to tune in a specific channel.