10.1 From CISC to RISC
Historically, when memory cycle times were very long and when memory prices were high, fewer, complicated instructions held an advantage over more, simpler instructions. There came a point, however, when memory became inexpensive enough and memory hierarchies became fast and large enough, that computer architects began reexamining this advantage. One technology that affected this examination was pipelining—that is, keeping the execution unit more or less the same, but allowing different instructions (which each require several clock cycles to execute) to use different parts of the execution unit on each clock cycle. For example, one instruction might be accessing operands in the register file while another is using the ALU.
We will cover pipelining in more detail later in the chapter, but the important point to make here is that computer architects learned that CISC instructions do not fit pipelined architectures very well. For pipelining to work effectively, each instruction needs to have similarities to other instructions, at least in terms of relative instruction complexity. The reason can be viewed in analogy to an assembly line that produces different models of an automobile. For efficiency, each “station” of the assembly line should do approximately the same amount and kind of work. If the amount or kind of work done at each station is radically different for different models, then periodically the assembly line will have to “stall” to accommodate the requirements of the given model.
CISC instruction sets have the disadvantage that some instructions, such as register-to-register moves, are inherently simple, whereas others, such as the MVC instruction and others like it are complex, and take many more clock cycles to execute.
The main philosophical underpinnings of the RISC approach are:
• Prefetch instructions into an instruction queue in the CPU before they are needed. This has the effect of hiding the latency associated with the instruction fetch.
• With instruction fetch times no longer a penalty, and with cheap memory to hold a greater number of instructions, there is no real advantage to CISC instructions. All instructions should be composed of sequences of RISC instructions, even though the number of instructions needed may increase (typically by as much as 1/3 over a CISC approach).
• Moving operands between registers and memory is expensive, and should be minimized.
• The RISC instruction set should be designed with pipelined architectures in mind.
• There is no requirement that CISC instructions be maintained as integrated wholes; they can be decomposed into sequences of simpler RISC instructions.
The result is that RISC architectures have characteristics that distinguish them from CISC architectures:
• All instructions are of fixed length, one machine word in size.
• All instructions perform simple operations that can be issued into the pipe- line at a rate of one per clock cycle. Complex operations are now composed of simple instructions by the compiler.
• All operands must be in registers before being operated upon. There is a separate class of memory access instructions: LOAD and STORE. This is referred to as a LOAD-STORE architecture.
• Addressing modes are limited to simple ones. Complex addressing calculations are built up using sequences of simple operations.
• There should be a large number of general registers for arithmetic operations so that temporary variables can be stored in registers rather than on a stack in memory.
In the next few sections, we explore additional motivations for RISC architectures, and special characteristics that make RISC architectures effective.