8085 Interrupts
1. Mention the interrupt pins of 8085.
Ans. There are five (5) interrupt pins of 8085—from pin 6 to pin 10. They represent TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR interrupts respectively. These five interrupts are ‘hardware’ interrupts.
2. Explain maskable and non-maskable interrupts.
Ans. An interrupt which can be disabled by software means, is called a maskable interrupt.
Thus an interrupt which cannot be masked is an unmaskable interrupt.
3. Which is the non maskable interrupt for 8085?
Ans. TRAP interrupt is the non-maskable interrupt for 8085. It means that if an interrupt comes via TRAP, 8085 will have to recognise the interrupt.
4. Do the interrupts of 8085 have priority?
Ans. Yes, the interrupts of 8085 have their priorities fixed—TRAP interrupt has the highest priority, followed by RST 7.5, RST 6.5, RST 5.5 and lastly INTR.
5. What is meant by priority of interrupts?
Ans. It means that if 8085 is interrupted by more than one interrupt at the same time, the one which is having highest priority will be serviced first, followed by the one(s) which is (are) having just next priority and so on.
For example, if 8085 is interrupted by RST 7.5, INTR and RST 5.5 at the same time,
then the sequence in which the interrupts are going to be serviced are as follows: RST
7.5, RST 5.5 and INTR respectively.
6. Mention the types of interrupts that
8085 supports.
Ans. 8085 supports two types of interrupts— hardware and software interrupts.
7. What are the software interrupts of 8085? Mention the instructions, their hex codes and the corresponding vector addresses.
Ans. 8085 has eight (8) software interrupts from RST 0 to RST 7. The instructions, hex codes and the vector locations are tabulated in Table 4.1:
Table 4.1: Vector addresses for software interrupts
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8. How the vector address for a software interrupt is determined?
Ans. The vector address for a software interrupt is calculated as follows:
Vector address = interrupt number × 8
For example, the vector address for RST 5 is calculated as
5 × 8 = 40)10 = 28)H
Vector address for RST 5 is 0028H.
9. In what way INTR is different from the other four hardware interrupts? Ans. There are two differences, which are discussed below:
1. While INTR is not a vectored interrupt, the other four, viz., TRAP, RST 7.5, RST
6.5 and RST 5.5 are all vectored interrupts. Thus whenever an interrupt comes via any one of these four interrupts, the internal control circuit of 8085 produces a CALL to a predetermined vector location. At these vector locations the subroutines are written.
On the other hand, INTR receives the address of the subroutine from the external
device itself.
2. Whenever an interrupt occurs via TRAP, RST 7.5, RST 6.5 or RST 5.5, the corresponding returns address (existing in program counter) is auto-saved in STACK, but this is not so in case of INTR interrupt.
10. Indicate the nature of signals that will trigger TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR.
Ans. TRAP interrupt is both positive edge and level triggered, RST 7.5 is positive edge triggered while RST 6.5, RST 5.5 and INTR are all level triggered.
11. Why the TRAP input is edge and level sensitive?
Ans. TRAP input is edge and level sensitive to avoid false triggering caused by noise and transients.
12. Draw the TRAP interrupt circuit diagram and explain the same.
Ans.
The positive edge of the TRAP signal sets the D F/F, so that Q becomes 1. It thus enables the AND gate, but the AND gate will output a 1 for a sustained high level at the TRAP input. In that case the subroutine written at vector memory location 2400H corresponding to TRAP interrupt starts executing. 2400H is the starting address of an interrupt service routine for TRAP.
There are two ways to clear the TRAP interrupt:
1. When the microprocessor is resetted, then via the inverter, a high comes out of the OR gate, thereby clearing the D F/F, making Q = 0.
2. When a TRAP is acknowledged by the system, an internal TRAP ACKNOWLEDGE is generated thereby clearing the D F/F.
13. Discuss the INTR interrupt of 8085.
Ans. The following are the characteristics of INTR interrupt of 8085:
*It is a maskable interrupt
* It has lowest priority
* It is a non-vectored interrupt.
Sequentially, the following occurs when INTR signal goes high:
1. 8085 checks the status of INTR signal during execution of each instruction.
2. If INTR signal remains high till the completion of an instruction, then 8085 sends
out an active low interrupt acknowledge (INTA) signal.
3. When INTA signal goes low, external logic places an instruction OPCODE on the
data bus.
4. On receiving the instruction, 8085 saves the address of next instruction (which would have otherwise been executed) in the STACK and starts executing the ISS (interrupt service subroutine).
14. Draw the diagram that outputs RST 3 instruction opcode on acknowledging the interrupt.
Ans. The diagram is shown below:
When an INTR is acknowledged by the microprocessor, it outputs a low INTA . Thus
an RST 3 is gated onto the system bus. The processor then first saves the PC in the STACK and branches to the location 0018H. At this address, the ISS begins and ends with a RET instruction. On encountering RET instruction in the last line of the ISS, the return address saved in the stack is restored in the PC so that normal processing in the main program (at the address which was left off when the program branched to ISS) begins.
15. What is to be done if a particular part of a program is not to be interrupted by RST 7.5, RST 6.5, RST 5.5 and INTR?
Ans. Two software instructions—EI and DI are used at the beginning and end of the particular portion of the program respectively. The scheme is shown schematically as follows:
16. Explain the software instructions EI and DI.
Ans. The EI instruction sets the interrupt enable flip-flop, thereby enabling RST 7.5, RST 6.5, RST 5.5 and INTR interrupts.
The DI instruction resets the interrupt enable flip-flop, thereby disabling RST 7.5, RST 6.5, RST 5.5 and INTR interrupts.
17. When returning back to the main program from Interrupt Service Subroutine (ISS), the software instruction EI is inserted at the end of the ISS. Why?
Ans. When an interrupt (either via RST 7.5, RST 6.5, RST 5.5, INTR) is acknowledged by the microprocessor, ‘any interrupt acknowledge’ signal resets the interrupt enable F/F. It thus disables RST 7.5, RST 6.5, RST 5.5 and INTR interrupts. Thus any future interrupt coming via RST 7.5, RST 6.5, RST 5.5 or INTR will not be acknowledged unless the software instruction EI is inserted which thereby sets the interrupt enable F/F.
18. Mention the ways in which the three interrupts RST 7.5, RST 6.5 and RST 5.5 are disabled?
Ans. The three interrupts can be disabled in the following manner:
*Software instruction DI
* RESET IN signal
*Any interrupt acknowledge signal.
19. Draw the SIM instruction format and discuss.
Ans. The SIM instruction format is shown below:
D7 and D6 bits are utilised for serial outputting of data from accumulator. D5 bit is a don’t care bit, while bits D4–D0 are used for interrupt control.
D4 bit can clear the D F/F associated with RST 7.5.
D3 bit is mask set enable (MSE) bit, while bits D2–D0 are the masking bits
corresponding to RST 7.5, RST 6.5 and RST 5.5 respectively.
None of the flags are affected by SIM instruction.
By employing SIM instruction, the three interrupts RST 7.5, RST 6.5 and RST 5.5 can be masked or unmasked. For masking any one of these three interrupts, MSE (i.e., bit D3) bit must be 1.
For example let RST 7.5 is to be masked (disabled), while RST 6.5 and RST 5.5 are
to be unmasked (enabled), then the content of the bits of the SIM instruction will be like 0000 1100 = 0CH
For this to be effective the following two instructions are written,
MVI A, 0CH SIM
Execution of SIM instruction allows copying of the contents of the accumulator into
the interrupt masks.
20. Show the RIM instruction format and discuss the same. Ans. RIM stands for ‘Read interrupt mask’ and its format is as follows:
When RIM instruction is executed in software, the status of SID, pending interrupts and interrupt masks are loaded into the accumulator. Thus their status can be monitored. It may so happen that when one interrupt is being serviced, other interrupt(s) may occur. The status of these pending interrupts can be monitored by the RIM instruction. None of the flags are affected by RIM instruction.
21. Write a program which will call the interrupt service subroutine (at 3C00H) corresponding to RST 7.5 if it is pending. Let the ACC content is 20 H on executing the RIM instruction.
Ans. The program for the above will be as hereunder:
22. Write a program which will call the subroutine (say named ‘SR’) if RST 6.5 is masked. Let content of ACC is 20 H on executing the RIM instruction.
Ans. RST 6.5 is masked if bit M¢6.5 (D1 bit of RIM) is a 1 and also D3 bit (i.e., IE) is 1 The program for the above will be as hereunder:
23. For what purpose TRAP interrupt is normally used?
Ans. TRAP interrupt is a non-maskable one i.e., if an interrupt comes via the TRAP input, the system will have to acknowledge that. That is why it is used for vital purposes which require immediate attention like power failure.
If the microprocessor based system loses power, the filter capacitors hold the supply voltage for several mili seconds.
During this time, data in the RAM can be written in a disk or E2PROM for future
usage.
24. Draw the interrupt circuit diagram for 8085 and explain.
Ans. Figure 4.6 is the interrupt circuit diagram of 8085. It shows the five hardware interrupts TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR along with the software interrupts RST n: n = 0 to 7.
Trap is both edge and level sensitive interrupt. A short pulse should be applied at the
trap input, but the pulse width must be greater than a normal noise pulse width and also long enough for the µP to complete its current instruction. The trap input must come down to low level for it to be recognised for the second time by the system. It is having highest priority.
Next highest priority interrupt is RST 7.5 which responds to the positive edge
(low to high transition) of a pulse. Like trap, it also has a D F/F whose output becomes 1 on accepting the RST 7.5 input, but final call to vector location 3C00H is reached only if RST 7.5 remains unmasked and the program has an EI instruction inserted already. These are evident from the circuit. If R 7.5 (bit D4 of SIM instruction) is 1, then RST 7.5 instruction will be overlooked i.e., it can override any RST 7.5 interrupt.
Like RST 7.5, final call locations 3400H and 2C00H corresponding to interrupts at RST 6.5 and RST 5.5 are reached only if the two interrupts remain unmasked and the software instruction EI is inserted.
The three interrupts RST 7.5, RST 6.5 and RST 5.5 are disabled once the system accepts an interrupt input via any one of these pins—this is because of the generation of ‘any interrupt acknowledge’ signal which disables them.
Any of the software RST instructions (RST n : n = 0 to 7) can be utilised by using
INTR instruction and hardware logic. RST instructions are utilised in breakpoint service routine to check register(s) or memory contents at any point in the program.
25. The process of interrupt is asynchronous in nature. Why?
Ans. Interrupts may come and be acknowledged (provided masking of any interrupt is not done) by the microprocessor without any reference to the system clock. That is why interrupts are asynchronous in nature.
26. In how many categories can ‘interrupt requests’ be classified?
Ans. The ‘interrupt requests’ can be classified into two categories—maskable interrupt and non-maskable interrupt.
A maskable interrupt can either be ignored or delayed as per the needs of the system
while a non-maskable interrupt has to be acknowledged.
27. When the interrupt pins of 8085 are checked by the system?
Ans. Microprocessor checks (samples) interrupt pins one cycle before the completion of an instruction cycle, on the falling edge of the clock pulse. An interrupt occurring at least 160 ns (150 ns for 8085A-2, since it is faster in operation) before the sampling time is treated as a valid interrupt.
28. Is there a minimum pulse width required for the INTR signal?
Ans. Microprocessor issues a low INTA signal as an acknowledgement on receiving an INTR interrupt input signal. A CALL instruction is then issued so that the program branches to Interrupt Service Subroutine (ISS). Now the CALL requires 18 T-states to complete. Hence the INTR pulse must remain high for at least 17.5 T-states. If 8085 is operated at 3 MHz clock frequency, then the INTR pulse must remain high for at least 5.8 mS.
29. Can the microprocessor be interrupted before completion of existing Interrupt Service Subroutine (ISS)?
Ans. Yes, the microprocessor can be interrupted before the completion of the existing ISS.
Let after acknowledging the INTR, the microprocessor is in the ISS executing instructions one by one. Now, for a given situation, if the interrupt system is enabled (by inserting an EI instruction) just after entering the ISS, the system can be interrupted again while it is in the first ISS.
If an interrupt service subroutine be interrupted again then this is called ‘nested interrupt’.
30. Bring out one basic difference between SIM and DI instructions.
Ans. While by using SIM instruction any combinations or all of RST 7.5, RST 6.5 and RST 5.5 can be disabled, on the other hand DI disables RST 7.5, RST 6.5, RST 5.5 and in addition INTR interrupt also.
31. What is RIM instruction and what does it do?
Ans. The instruction RIM stands for Read Interrupt Mask. By executing this instruction in software, it is possible to know the status of interrupt mask, pending interrupt(s), and serial input.
32. In an interrupt driven system, EI instruction should be incorporated at the beginning of the program. Why?
Ans. A program, written by a programmer in the RAM location, is started first by system reset and loading the PC with the starting address of the program.
Now, with a system reset, all maskable interrupts are disabled. Hence, an EI
instruction must be put in at the beginning of the program so that the maskable interrupts, which should remain unmasked in a program, remain so.
33. How the system can handle multiple interrupts?
Ans. Multiple interrupts can be handled if a separate interrupt is allocated to each peripheral.
The programmable interrupt controller IC 8259 can also be used to handle multiple interrupts when they are interfaced through INTR.
34. When an interrupt is acknowledged, maskable interrupts are automatically disabled. Why?
Ans. This is done so that the interrupt service subroutine (ISS) to which the program has entered on receiving the interrupt, has a chance to complete its own task.
35. What is meant by ‘nested interrupts’? What care must be taken while handling nested interrupts?
Ans. Interrupts occurring within interrupts are called ‘nested interrupts’.
While handling nested interrupts, care must be taken to see that the stack does not grow to such an extent as to foul the main program—in that case the system program fails.
36. ‘A RIM instruction should be performed immediately after TRAP occurs’—Why?
Ans. This is so as to enable the pre-TRAP interrupt status to be restored with the implementation of a SIM instruction.
37. What does the D4 bit of SIM do?
Ans. Bit D4 of SIM is R 7.5 which is connected to RST 7.5 F/F via a OR gate. If D4 of SIM is made a 1, then it resets RST 7.5 F/F. This thus can be used to override RST 7.5 without servicing it.
38. Comment on the TRAP input of 8085.
Ans. Trap input is both edge and level sensitive. It is a narrow pulse, but the pulse width should be more than normal noise pulse width. This is done so that noise cannot affect the TRAP input with a false triggering. Again the pulse width should be such that the TRAP input which is directly connected to the gate stays high till the completion of current instruction by the mP. In that case, only the program gets diverted to vector call location 2400 H.
TRAP cannot respond for a second time until the first TRAP goes through a high to low transition.
TRAP interrupt, once acknowledged, goes to 2400 H vector location without any external hardware or EI instruction, as is the case for other interrupt signals to be acknowledged.
39. Discuss about the triggering levels of RST 7.5, RST 6.5 and RST 5.5.
Ans. RST 7.5 is positive edge sensitive and responds to a short trigger pulse. The interrupt that comes via RST 7.5 is stored in a D F/F, internal to mP. The final vector call location 3C00 H is invoked only if RST 7.5 remains unmasked via SIM and software instruction EI is inserted in the program.
RST 6.5 and 5.5 respond to high level (i.e., level sensitive) at their input pins—thus these two pins must remain high until microprocessor completes the execution of the current instruction.
40. Discuss the utility of RST software instruction.
Ans. For an RST instruction (RST n, n : 0 to 7) to become effective, external hardware is necessary, along with INTR interrupt instruction.
When debugging is required in a program to know the register(s) or memory contents, breakpoints are inserted via RST instruction.
A breakpoint is an RST instruction inserted in a program. When an RST instruction is recognised, the program control is transferred to the corresponding RST vector location. From this vector location, it is again transferred to the breakpoint service routine so that programmer can check the contents of any register or memory content on pressing specified key(s). After testing, the routine returns to the breakpoint in the main program.
Thus RST instructions can be inserted within a program to examine the register/
memory content as per the requirement.
41. Under what condition, an RST instruction is going to be recognised?
Ans. Any RST instruction is recognised only if the EI instruction is incorporated via software.
42. Can the ‘TRAP’ interrupt be disabled by a combination of hardware and software?
Ans. Yes, it can be disabled by SIM instruction and hardware, as shown in Fig. 4.7.
The following two instructions are executed.
MVIA, 40 H
SIM
It ensures that a ‘0’ logic comes out via SOD pin (pin 4) of 8085. This is then ANDed with TRAP input.
Thus pin 6 (TRAP) always remains at ‘0’ logic and hence TRAP input is disabled or ‘MASKED’.
43. Level wise, how the interrupts can be classified? Distinguish them.
Ans. Level wise, interrupts can be classified as
1 single level interrupts
2 multi level interrupts
Their distinguishing features are shown below:
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Single level interrupt |
Multi level interrupt |
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1. Interrupts are fed via a single pin of microprocessor (like INTR of 8085) 2. CPU polls the I/O devices to identify the interrupting device. 3. Slower because of sl. no. 2. |
1. Interrupts are fed via different pins of microprocessor (like RST 7.5, RST 6.5 etc), each interrupt requiring a separate pin of microprocessor. 2. Since each interrupt pin corresponds to a single I/O device, polling is not necessary. 3. Faster because of sl. no. 2. |