5.9 SOME QUESTIONS AND ANSWERS
During the discussion of interfacing I/O devices, we focused on the basic concepts and avoided some details in order to simplify the presentation. We will now attempt to answer some of those questions.
1. What are the other I/O instructions in the Z80 instruction set, and how do they differ from the I/O instructions discussed here?
The Z80 instruction set includes six output instructions, of which we discussed only one. The remaining five instructions perform various types of output functions: for example, output a byte from any of the registers or from a memory location, or output a block of memory. In these instructions, register C is used to specify the port address and register B can be used as a counter.
2. What are the contents of the high-order bus (A15-A8) during the M3 cycle of the INIOUT instructions?
The contents of the high-order bus during the M3 cycle of the I/O instructions, illustrated in Sections 5.1 and 5.3, are generally irrelevant to the interfacing of I/O devices. For the I/O instructions discussed, the contents of the accumulator are placed on the A15-A8 bus. However, in other I/O instructions where the contents of register C are used to specify a port address, the contents of register B are placed on the high-order bus.
3. Why is one Wait state automatically inserted when an I/O instruction is executed?
When an I/O instruction is being executed, the control signal I̅O̅R̅Q̅ is asserted during T2, of the M3 cycle. This does not leave sufficient time for the Z80 to sample the WAIT line. Therefore, a slow-responding I/O device would not be able to decode its address and activate the WAIT line if necessary. Adding one Wait cycle allows the device to activate the WAIT signal for additional Wait states.
4. In a memory-mapped I/O, what is the reason for not automatically inserting a Wait state?
In the Memory Read/Write cycles, the M̅R̅E̅Q̅ is asserted during T1; therefore, there is sufficient time to sample the WAIT line during T2 state.
5. In a memory-mapped I/O, how does the microprocessor differentiate between I/O and memory, and can an I/O device have the same address as a memory register?
In the memory-mapped I/O, the microprocessor cannot differentiate be tween an I/O device and memory; it treats an I/O device as if it is memory. Therefore, an I/O device and memory register cannot have the same address; the entire memory map (64K) of the system has to be shared between memory and I/O.
6. Why is a I6-bit address (data) stored in memory in the reversed order, i.e., the low-order byte first, followed by the high-order byte?
In the Z80 microprocessor, the instruction decoder and the associated microprogram are designed to recognize the second byte as the low-order byte in a 3-byte instruction.