Electro-Thermal Model of Power Semiconductors Dedicated for Both Case and Junction Temperature Estimation

The thermal model for power semiconductors devices from junction to ambient can be modeled by a series thermal resistance Rth and capacitance Cth networks [13]. The power loss generated on the semiconductor junction or chips first flows through the internal thermal networks of power device to its case or base plate, and then the left power loss continues going through the attached thermal grease and heat sink until the ambient. When the loss passes though the thermal network outside power devices, the case temperature is then established; when the loss passes though the thermal network inside power devices, the junction temperature will be established based on the case temperature level.

As a study case, the power semiconductor device of IGBT module is applied in a typical three-phase DC-AC two-level voltage source converter. The rated power of converter is set as 1 MW with unit power factor, the input DC voltage is 1100 V and output line to line voltage is 690 Vrms, switching frequency of IGBT module is designed at 1950 Hz. IGBT module 5SNA1600N170100 (1600 A/1700 V) from ABB [4, 5] is chosen with enough datasheet information for thermal analysis.

Normally the multilayer Foster thermal RC network inside the IGBT module (i.e. from junction to case) is widely provided by manufacturers on their device datasheets. This type of thermal model is just a mathematical fitting of the measured external thermal behavior of power device and don’t represent any physical meaning for each RC layer [1, 3, 6]. As an example to demonstrate the limits of the Foster thermal network, a complete thermal impedance train including thermal networks inside and outside the given IGBT module is shown in Fig. 10.1.

Based on the thermal impedance in Fig. 10.1. and the given converter condition, (Fig. 10.2) the simulated power loss generated inside individual IGBT Pin, power loss output from IGBT base plate Pout, as well as the IGBT junction and case temperature Tj and TC are shown in Fig. 10.3a respectively. It is noted that the Pin which is periodically changed at 50 Hz with many switching loss pulses trans- parently passes through the internal Foster thermal network of power device (i.e. Pin = Pout). When the un-filtered power loss Pout passes through the thermal

Electro-Thermal Model of Power Semiconductors Dedicated for Both Case and Junction Temperature Estimation-0126

resistance of the thermal grease, abrupt changed IGBT case temperature TC as well as the junction temperature Tj are observed. Therefore, the Foster thermal RC network inside IGBT module should be only connected to a temperature reference and cannot be extended with any other thermal RC networks like the thermal grease or heat sink, this limit is also introduced and described in [1, 3].

In order to estimate the correct case and junction temperature by the given power semiconductor devices and the corresponding heat sink design, the Foster thermal network inside IGBT module has to be mathematically transferred to the equivalent Cauer type RC network. As shown in Fig. 10.2, in which the thermal impedance inside IGBT module are replaced by the equivalent multilayer Cauer RC network. The corresponding power loss generated inside individual IGBT Pin, power loss output from IGBT base plate Pout, as well as the IGBT junction and case temperature Tj and TC are shown in Fig. 10.3b respectively. It is noted that the unregulated loss pulses of Pin are significantly filtered into smooth Pout by the parallel multilayer thermal capacitances inside IGBT module, a much more stable case temperature TC is thereby established compared to Fig. 10.3a and a correct device junction temperature Tj profile at steady state can be observed.

However, the mathematical transformation from Foster to Cauer thermal net-work does not gain any physical meaning for each RC layer either, this means the Pin in Fig. 10.3b may not be correctly filtered by the equivalent Cauer thermal model. Normally over-filtering will be introduced when doing the mathematically transformation from Foster to Cauer form (it can be verified from Fig. 10.3b that there is almost no fluctuation in Pout) [6], and this over-filtering in the equivalent multilayer Cauer network will lead to slower dynamic performance for the Pout and eventually for the case temperature TC and junction temperature Tj estimation of power devices.

A new thermal model which targets to overcome the shortages of this two thermal models are given in this topic. The proposed thermal model is shown in Fig. 10.4, it can be seen that it looks like a combined solution and contains two paths for the thermal flow:

The first thermal path is used for the junction temperature estimation. In this path the original datasheet-based multilayer Foster thermal network inside power devi- ces are used. Different from Fig. 10.1, only a temperature potential, whose value is

Electro-Thermal Model of Power Semiconductors Dedicated for Both Case and Junction Temperature Estimation-0127

determined by the case temperature TC from the other thermal path, is connected to the Foster network. As a result the abrupt change of case temperature and junction temperature in the thermal model of Fig. 10.1 can be avoided.

The second thermal path is used for the case and heat sink temperature estimation. In this path the thermal network inside IGBT module is just used for the Pin loss filtering rather than the junction temperature estimation. While the complete thermal network outside IGBT module (i.e. thermal grease and heat sink) have to be included. It is noted that the multilayer Foster thermal network inside IGBT module is mathematically transformed to a Single-layer Cauer RC unit. This transformation will lose some accuracy for the dynamic performance of junction temperature Tj, but the physical meaning is somehow regained because any object can be represented as a Cauer RC unit from the thermal point of view, consequently, the single-layer equivalent Cauer RC unit inside the IGBT module can achieve more correct filtering of Pin, and better dynamic performance for the Pout and TC com- pared to the multilayer equivalent Cauer network in Fig. 10.2.

When applying the proposed thermal model, the corresponding power loss generated inside individual IGBT Pin, power loss output from IGBT base plate Pout, as well as the IGBT junction and case temperature Tj and TC are shown in Fig. 10.5a respectively, in which the behaviors of the equivalent Cauer thermal model in Fig. 10.2 are also indicated as a comparison. It can be seen that under the same generated power loss Pin, the proposed new thermal model can achieve almost the same junction and case temperatures as the Cauer thermal model in Fig. 10.2 at steady state, the Pout and TC are less filtered (or more fluctuated) in the new thermal model.

Electro-Thermal Model of Power Semiconductors Dedicated for Both Case and Junction Temperature Estimation-0128

Figure 10.5b shows a dynamic change of the converter loading from rated 1 MW power output to 0.2 MW output at the 0.6 s. It can be seen that the new thermal model can achieve faster response in the Pout, TC and Tj.

Conclusion

The Foster thermal model and the equivalent Cauer form both have their limits to correctly estimate the case and junction temperature of power semiconductor devices. By the proposed thermal model, it is possible to extend the Foster thermal network with other thermal impedances, and thereby acquire more accurate junction and case temperature of power semiconductor devices not only under steady state but also during dynamic thermal changes.

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