microcontrollers

Questions

Find the following using the information provided in Chapter 2.

1. Size of the internal RAM.

2. Internal ROM size in the 8031.

3. Execution time of a single byte instruction for a 6 megahertz crystal.

4. The 16-bit data addressing registers and their functions.

5. Registers that can do division.

6. The flags that are stored in the PSW.

7. Which register holds the serial data interrupt bits TI and RI.

8. Address of the stack when the 8051 is reset.

9. Number of register banks and their addresses.

10. Ports used for external memory access.

11. The bits that determine timer modes and the register that holds these bits.

12. Address of a subroutine that handles a timer 1 interrupt.

13. Why a low-address byte latch for external memory is needed.

14. How an 1/0 pin can be both an input and output.

15. Which port has no alternate functions.

16. The maximum pulse rate that can be counted on pin T1 if the oscillator frequency is 6 megahertz.

17. Which bits in which registers must be set to give the serial data interrupt the highest

priority.

18. The baud rate for the serial port in mode 0 for a 6 megahertz crystal.

19. The largest possible time delay for a timer in mode I if a 6 megahertz crystal is used.

20. The setting of TH1. in timer mode 2, to generate a baud rate of 1200 if the serial port is in mode I and an 11.059 megahertz crystal is in use. Find the setting for both values of SMOD.

21. The address of the PCON special-function register.

22. The time it will take a timer in mode I to overflow if initially set to 03AEh with a 6 megahertz crystal.

23. Which bits in which registers must be set to 1 to have timer 0 count input pulses on pin

T0 in timer mode 0.

24. The register containing GF0 and GF1.

25. The signal that reads external ROM.

26. When used in multiprocessing. which bit in which register is used by a transmitting 8051 to signal receiving 805’s that an interrupt should be generated.

27. The two conditions under which program opcodes are fetched from external, rather than internal, memory.

28. Which bits in which register(s) must be set to make (INTO)’ level activated, and (INT1)’ edge triggered.

29. The address of the interrupt program for the (INTO)’ level-generated interrupt.

30. The bit address of bit 4 of RAM byte 2Ah.

Summary

The internal hardware configuration of the 8051 registers and control circuits have been examined at the functional block diagram level. The 8051 may be considered to be a col­lection of RAM, ROM, and addressable registers that have some unique functions.

SPECIAL-FUNCTION REGISTERS

EXTERNAL CONNECTION PINS

                          Function

Port pins 36 I/O, external memory, interrupts

Oscillator 2     Clock

Power 2

Interrupts

A computer program has only two ways to determine the conditions that exist in internal and external circuits. One method uses software instructions that jump on the states of flags and port pins. The second responds to hardware signals. called interrupts. that force the program to call a sub-routine. Software techniques use up processor time that could be devoted to other tasks; interrupts take processor time only when action by the program is needed. Most applications of microcontrollers involve responding to events quickly enough to control the environment that generates the events (generically termed "real-

FIGURE 17 IE and IP Function Registers

THE INTERRUPT ENABLE (IE) SPECIAL FUNCTION REGISTER

Bit addressable as IE.0 to IE.7

THE INTERRUPT PRIORITY (IP) SPECIAL FUNCTION REGISTER

Note: Priority may be 1 (highest) or 0 (lowest)

Bit addressable as IP.O to IP.7

time programming"). Interrupts are often the only way in which real-time programming can be done successfully.

Interrupts may be generated by internal chip operations or provided by external sources. Any interrupt can cause the 8051 to perform a hardware call to an interrupt-­handling subroutine that is located at a predetermined (by the 8051 designers) absolute address in program memory.

Five interrupts are provided in the 8051 . Three of these are generated automatically by internal operations: timer flag 0, timer flag 1, and the serial port interrupt (RI or TI). Two interrupts are triggered by external signals provided by circuitry that is connected to pins (INT0)’ and (INT1)’ (port pins P3.2 and P3.3).

All interrupt functions are under the control of the program. The programmer is able to alter control bits in the interrupt enable register (IE), the interrupt priority register (IP), and the timer control register (TCON). The program can block all or any combination of the interrupts from acting on the program by suitably setting or clearing bits in these regis­ters. The IE and IP registers are shown in Figure 17.

After the interrupt has been handled by the interrupt subroutine, which is placed by the programmer at the interrupt location in program memory, the interrupted program must resume operation at the instruction where the interrupt took place. Program resump­tion is done by storing the interrupted PC address on the stack in RAM before changing the PC to the interrupt address in ROM. The PC address will be restored from the stack after an RETI instruction is executed at the end of the interrupt subroutine.

Timer Flag Interrupt

When a timer/counter overflows, the corresponding timer flag, TF0 or TF1, is set to 1. The flag is cleared to 0 when the resulting interrupt generates a program call to the appro­priate timer subroutine in memory.

Serial Port Interrupt

If a data byte is received, an interrupt bit, RI, is set to 1 in the SCON register. When a data byte has been transmitted an interrupt bit, TI, is set in SCON. These are ORed together to provide a single interrupt to the processor: the serial port interrupt. These bits are not cleared when the interrupt-generated program call is made by the processor. The program that handles serial data communication must reset RI or TI to 0 to enable the next data communication operation.

External Interrupts

Pins (INT0)’ and (INT1)’ are used by external circuitry. Inputs on these pins can set the inter­rupt flags lE0 and IE1 in the TCON register to 1 by two different methods. The IEX flags may be set when the (INTX)’ pin signal reaches a low level, or the flags may be set when a high-to-low transition takes place on the (INTX)’ pin. Bits ITO and ITI in TCON program the (INTX)’ pins for low-level interrupt when set to 0 and program the (INTX)’ pins for transi­tion interrupt when set to 1 .

Flags IEX will be reset when a transition-generated interrupt is accepted by the pro­cessor and the interrupt subroutine is accessed. It is the responsibility of the system de­signer and programmer to reset any level-generated external interrupts when they are serviced by the program. The external circuit must remove the low level before an RET1 is executed. Failure to remove the low will result in an immediate interrupt after RET1 , from the same source.

Reset

A reset can be considered to be the ultimate interrupt because the program may not block the action of the voltage on the RST pin. This type of interrupt is often called "non-­maskable," since no combination of bits in any register can stop, or mask the reset action. Unlike other interrupts, the PC is not stored for later program resumption; a reset is an absolute command to jump to program address 0000h and commence running from there.

Whenever a high level is applied to the RST pin, the 8051 enters a reset condition.

After the RST pin is brought low, the internal registers will have the values shown in the following table:

Internal RAM is not changed by a reset; however, the states of the internal RAM when power is first applied to the 8051 are random. Register bank 0 is selected upon reset as all hits in PSW are 0.

Interrupt Control

The program must be able, at critical times, to inhibit the action of some or all of the interrupts so that crucial operations can be finished. The IE register holds the program­mable bits that can enable or disable all the interrupts as a group, or if the group is en­abled, each individual interrupt source can be enabled or disabled.

Often, it is desirable to be able to set priorities among competing interrupts that may conceivably occur simultaneously. The IP register bits may be set by the program to assign priorities among the various interrupt sources so that more important interrupts can be serviced first should two or more interrupts occur at the same time.

Interrupt Enable/Disable

Bits in the EI register are set to 1 if the corresponding interrupt source is to be enabled and set to 0 to disable the interrupt source. Bit EA is a master, or "global," bit that can enable or disable all of the interrupts.

Interrupt Priority

Register IP bits determine if any interrupt is to have a high or low priority. Bits set to I give the accompanying interrupt a high priority while a 0 assigns a low priority. Interrupts with a high priority can interrupt another interrupt with a lower priority; the low priority interrupt continues after the higher is finished.

If two interrupts with the same priority occur at the same time, then they have the following ranking:

I. IE0

2. TF0

3. IE1

4. TF1

S. Serial = RI OR TI

The serial interrupt could be given the highest priority by setting the PS bit in IP to I, and all others to 0.

Interrupt Destinations

Each interrupt source causes the program to do a hardware call to one of the dedicated addresses in program memory. It is the responsibility of the programmer to place a routine at the address that will service the interrupt.

The interrupt saves the PC of the program, which is running at the time the interrupt is serviced on the stack in internal RAM. A call is then done to the appropriate memory location. These locations are shown in the following table:

A RETI instruction at the end of the routine restores the PC to its place in the inter­rupted program and resets the interrupt logic so that another interrupt can be serviced. Interrupts that occur but are ignored due to any blocking condition (IE bit not set or a higher priority interrupt already in process) must persist until they are serviced, or they will be lost. This requirement applies primarily to the level-activated (INTX)’ interrupts.

Software Generated Interrupts

When any interrupt flag is set to I by any means, an interrupt is generated unless blocked. This means that the program itself can cause interrupts of any kind to be generated simply by setting the desired interrupt flag to I using a program instruction.

Serial Data Input/Output

Computers must be able to communicate with other computers in modern multiprocessor distributed systems. One cost-effective way to communicate is to send and receive data bits serially. The 8051 has a serial data communication circuit that uses register SBUF to hold data. Register SCON controls data communication, register PCON controls data rates, and pins RXD (P3.0) and TXD (P3.1) connect to the serial data network.

SBUf is physically two registers. One is write only and is used to hold data to be transmitted out of the 8051 via TXD. The other is read only and holds received data from external sources via RXD. Both mutually exclusive registers use address 99h.

There are four programmable modes for serial data communication that are chosen by setting the SMX bits in SCON. Baud rates are determined by the mode chosen. Figure 13 shows the bit assignments for SCON and PCON.

Serial Data Interrupts

Serial data communication is a relatively slow process, occupying many milliseconds per data byte to accomplish. In order not to tie up valuable processor time, serial data flags are

FIGURE 13 SCON and PCON Function Registers

THE SERIAL PORT CONTROL (SCON) SPECIAL FUNCTION REGISTER

Bit addressable as SCON.O to SCON.7

THE POWER MODE CONTROL (PCON) SPECIAL FUNCTION REGISTER

included in SCON to aid in efficient data transmission and reception. Notice that data transmission is under the complete control of the program, but reception of data is unpre­dictable and at random times that are beyond the control of the program.

The serial data flags in SCON. T1 and R1, are set whenever a data byte is transmitted (T1) or received (R1). These flags are ORed together to produce an interrupt to the pro­gram. The program must read these flags to determine which caused the interrupt and then clear the flag. This is unlike the timer flags that are cleared automatically; it is the respon­sibility of the programmer to write routines that handle the serial data flags.

Data Transmission

Transmission of serial data bits begins anytime data is written to SBUF. T1 is set to a 1 when the data has been transmitted and signifies that SBUF is empty (for transmission purposes) and that another data byte can be sent. If the program fails to wait for the T1 flag and overwrites SBUF while a previous data byte is in the process of being transmitted, the results will be unpredictable (a polite term for "garbage out").

Data Reception

Reception of serial data will begin if the receive enable bit (REN) in SCON is set to 1 for all modes. In addition, for mode 0 only, R1 must be cleared to 0 also. Receiver interrupt flag R1 is set after data has been received in all modes. Setting REN is the only direct program control that limits the reception of unexpected data; the requirement that R1 also be 0 for mode 0 prevents the reception of new data until the program has dealt with the old data and reset R1.

Reception can begin in modes 1, 2, and 3 if R1 is set when the serial stream of bits begins. R1 must have been reset by the program before the last bit is received or the incoming data will be lost. Incoming data is not transferred to SBUF until the last data bit has been received so that the previous transmission can be read from SBUF while new data is being received.

Serial Data Transmission Modes

The 8051 designers have included four modes of serial data transmission that enable data communication to be done in a variety of ways and a multitude of baud rates. Modes are selected by the programmer by setting the mode bits SM0 and SM1 in SCON. Baud rates are fixed for mode 0 and variable, using timer 1 and the serial baud rate modify bit (SMOD) in PCON, for modes 1. 2. and 3.

Serial Data Mode 0-Shift Register Mode

Setting bits SM0 and SM 1 in SCON to 00b configures SBUF to receive or transmit eight data bits using pin RXD for both functions. Pin TXD is connected to the internal shift frequency pulse source to supply shift pulses to external circuits. The shift frequency, or baud rate, is fixed at 1/12 of the oscillator frequency, the same rate used by the timers when in the timer configuration. The TXD shift clock is a square wave that is low for machine cycle states S3-S4-S5 and high for S6-S1-S2. Figure 14 shows the timing for mode 0 shift register data transmission.

When transmitting, data is shifted out of RXD; the data changes on the falling edge of S6P2, or one clock pulse after the rising edge of the output TXD shift clock. The sys­tem designer must design the external circuitry that receives this transmitted data to re­ceive the data reliably based on this timing.

FIGURE 14 Shift Register Mode 0 Timing

Received data comes in on pin RXD and should be synchronized with the shift clock produced at TXD. Data is sampled on the Jailing edge of S5P2 and shifted in to SBUF on the rising edge of the shift clock.

Mode 0 is intended not for data communication between computers, but as a high­-speed serial data-collection method using discrete logic to achieve high data rates. The baud rate used in mode 0 will be much higher than standard for any reasonable oscillator frequency; for a 6 megahertz crystal, the shift rate will be 500 kilohertz.

Serial Data Mode 1-Standard UART

When SM0 and SM1 are set to 01b, SBUF becomes a 10-bit full-duplex receiver/ transmitter that may receive and transmit data at the same time. Pin RXD receives all data, and pin TXD transmits all data. Figure 15 shows the format of a data word.

Transmitted data is sent as a start bit, eight data bits (Least Significant Bit, LSB, first), and a stop bit. Interrupt flag T1 is set once all ten bits have been sent. Each bit interval is the inverse of the baud rate frequency, and each bit is maintained high or low over that interval.

Received data is obtained in the same order; reception is triggered by the falling edge of the start bit and continues if the stop bit is true (0 level) halfway through the start bit interval. This is an anti-noise measure; if the reception circuit is triggered by noise on the transmission line, the check for a low after half a bit interval should limit false data reception.

Data bits are shifted into the receiver at the programmed baud rate, and the data word will be loaded to SBUF if the following conditions are true: R1 must be 0, and mode bit SM2 is 0 or the stop bit is 1 (the normal state of stop bits). R1 set to 0 implies that the program has read the previous data byte and is ready to receive the next; a normal stop bit will then complete the transfer of data to SBUF regardless of the state of SM2. SM2 set to 0 enables the reception of a byte with any stop bit state, a condition which is of limited use in this mode, but very useful in modes 2 and 3. SM2 set to 1 forces reception of only "good" stop bits, an anti-noise safeguard.

Of the original ten bits, the start bit is discarded, the eight data bits go to SBUF. and the stop bit is saved in bit RB8 of SCON. R1 is set to 1, indicating a new data byte has been received.

FIGURE 15 Standard UART Data Word

If R1 is found to be set at the end of the reception, indicating that the previously received data byte has not been read by the program. or if the other conditions listed are not true, the new data will not be loaded and will be lost.

Mode 1 Baud Rates

Timer 1 is used to generate the baud rate for mode I by using the overflow flag of the timer to determine the baud frequency. Typically. timer I is used in timer mode 2 as an autoload R-hit timer that generates the baud frequency:

SMOD is the control hit in PCON and can be 0 or 1, which raises the 2 in the equation to a value of 1 or 2.

If timer 1 is not run in timer mode 2, then the baud rate is

and timer 1 can be run using the internal clock or as a counter that receives clock pulses from any external source via pin T1.

The oscillator frequency. is chosen to help generate both standard and nonstandard baud rates. If standard baud rates are desired, then an 11.0592 megahertz crystal could be selected. To get a standard rate of 9600 hertz then, the setting of TH 1 may be found as

follows:

if SMOD is cleared to 0 .

Serial Data Mode 2-Multiprocessor Mode

Mode 2 is similar to mode 1 except 11 bits are transmitted: a start bit, nine data bits. and a stop bit, as shown in Figure 16. The ninth data bit is gotten from bit TB8 in SCON during transmit and stored in bit RB8 of SCON when data is received. Both the start and stop bits are discarded.

The baud rate is programmed as follows:

figure 16 Multiprocessor Data Word

Here, as in the case for mode 0, the baud rate is much higher than standard communica­tion rates. This high data rate is needed in many multi-processor applications. Data can be collected quickly from an extensive network of communicating microcontrollers if high baud rates are employed.

The conditions for setting RI for mode 2 are similar to mode 1: RI must be 0 before the last bit is received, and SM2 must be 0 or the ninth data bit must be a 1. Setting RI based upon the state of SM2 in the receiving 8051 and the state of bit 9 in the transmitted message makes multiprocessing possible by enabling some receivers to be interrupted by certain messages, while other receivers ignore those messages. Only those 8051’s that have SM2 set to 0 will be interrupted by received data which has the ninth data bit set to 0; those with SM2 set to 1 will not be interrupted by messages with data bit 9 at 0. All receivers will be interrupted by data words that have the ninth data bit set to 1; the state of SM2 will not block reception of such messages.

This scheme allows the transmitting computer to "talk" to selected receiving comput­ers without interrupting other receiving computers. Receiving computers can be com­manded by the "talker" to "listen" or "deafen" by transmitting coded byte(s) with the ninth data bit set to 1 . The I in data bit 9 interrupts all receivers. instructing those that are programmed to respond to the coded byte(s) to program the state of SM2 in their respec­tive SCON registers. Selected listeners then respond to the bit 9 set to 0 messages. while all other receivers ignore these messages. The talker can change the mix of listeners by transmitting bit 9 set to 1 messages that instruct new listeners to set SM2 to 0, while others are instructed to set SM2 to 1 .

Serial Data Mode 3

Mode 3 is identical to mode 2 except that the baud rate is determined exactly as in mode 1 . using Timer I to generate communication frequencies.

Counters and Timers

Many microcontroller applications require the counting of external events, such as the frequency of a pulse train, or the generation of precise internal time delays between com­puter actions. Both of these tasks can be accomplished using software techniques, but software loops for counting or timing keep the processor occupied so that other, perhaps more important, functions are not done. To relieve the processor of this burden, two 16-bit up counters, named T0 and T1, are provided for the general use of the programmer. Each counter may be programmed to count internal clock pulses, acting as a timer, or pro­grammed to count external pulses as a counter.

bit addressable as TCON.0 to TCON.7

THE TIMER MODE CONTROL (TMOD) SPECIAL FUNCTION REGISTER

TMOD is not bit addressable

The counters are divided into two 8-bit registers called the timer low (TLO. TL I) and high (THO. TH I) bytes. All counter action is controlled by bit states in the timer mode control register (TMOD). the timer/counter control register (TCON). and certain program instructions.

TMOD is dedicated solely to the two timers and can be considered to be two duplicate 4-bit registers. each of which controls the action of one of the timers. TCON has control bits and Hags for the timers in the upper nibble. and control bits and Hags for the external interrupts in the lower nibble. Figure 10 shows the bit assignments for TMOD and TCON.

Timer Counter Interrupts

The counters have been included on the chip to relieve the processor of timing and count­ing chores. When the program wishes to count a certain number of internal pulses or external events, a number is placed in one of the counters. The number represents the maximum count less the desired count, plus one. The counter increments from the initial number to the maximum and then rolls over to zero on the final pulse and also sets a timer Hag. The Hag condition may be tested by an instruction to tell the program that the count has been accomplished, or the Hag may be used to interrupt the program.

figure 11  timer/counter control logic

Timing

If a counter is programmed to be a timer, it will count the internal clock frequency of the R051 oscillator divided by 12d. As an example, if the crystal frequency is 6.0 megahertz, then the timer clock will have a frequency of 500 kilohertz.

The resultant timer clock is gated to the timer by means of the circuit shown in Figure 11. In order for oscillator clock pulses to reach the timer, the CIT bit in the TMOD register must be set to 0 (timer operation). Bit TRX in the TCON register must be set to 1 (timer run), and the gate bit in the TMOD register must be 0, or external pin (INTX)’ must he a 1 . In other words, the counter is configured as a timer, then the timer pulses are gated to the counter by the run bit and the gate bit or the external input bits (INTX)’.

Timer Modes of Operation

The timers may operate in anyone of four modes that are determined by the mode bits, M I and MO, in the TMOD register. Figure 12 shows the four timer modes.

Timer Mode 0

Setting timer X mode bits to 00b in the TMOD register results in using the THX register as an 8-bit counter and TLX as a 5-bit counter; the pulse input is divided by 32d in TL so that TH counts the original oscillator frequency reduced by a total 384d. As an example, the 6 megahertz oscillator frequency would result in a final frequency to TH of 15625 hertz. The timer flag is set whenever THX goes from FFh to 00h, or in .0164 seconds for a 6 megahertz crystal if THX starts at 00h.

Timer Mode 1

Mode 1 is similar to mode 0 except TLX is configured as a full 8-bit counter when the mode bits are set to 0lb in TMOD. The timer flag would be set in .1311 seconds using a 6 megahertz crystal.

FIGURE 12 Timer 1 and Timer a Operation Modes

Timer Mode 2

Setting the mode bits to l0b in TMOD configures the timer to use only the TLX counter as an 8-bit counter. THX is used to hold a value that is loaded into TLX every time TLX overflows from FFh to 00h. The timer flag is also set when TLX overflows.

This mode exhibits an auto-reload feature: TLX will count up from the number in THX. overflow. and be initialized again with the contents of THX. For example. Placing 9Ch in THX will result in a delay of exactly .0002 seconds before the overflow flag is set if a 6 megahertz crystal is used.

Timer Mode 3

Timers 0 and 1 may be programmed to be in mode 0, 1, or 2 independently of a similar mode for the other timer. This is not true for mode 3; the timers do not operate indepen­dently if mode 3 is chosen for timer 0. Placing timer I in mode 3 causes it to stop count­ing; the control bit TRI and the timer I flag TFI are then used by timer 0.

Timer 0 in mode 3 becomes two completely separate 8-bit counters. TL0 is controlled by the gate arrangement of Figure 11 and sets timer flag TF0 whenever it overflows from FFh to 00h. TH0 receives the timer clock (the oscillator divided by 12) under the control of TR 1 only and sets the TF1 flag when it overflows.

Timer 1 may still be used in modes 0, 1, and 2, while timer 0 is in mode 3 with one important exception: No interrupts will be generated by timer I while timer 0 is using the TF1 overflow flag. Switching timer I to mode 3 will stop it (and hold whatever count is in timer 1). Timer 1 can be used for baud rate generation for the serial port, or any other mode 0, 1, or 2 function that does not depend upon an interrupt (or any other use of the TF1 flag) for proper operation.

Counting

The only difference between counting and timing is the source of the clock pulses to the counters. When used as a timer, the clock pulses are sourced from the oscillator through the divide-by-12d circuit. When used as a counter, pin T0 (P3.4) supplies pulses to counter 0. and pin T1 (P3.5) to counter 1 . The C/(T)’ bit in TMOD must be set to 1 to enable pulses from the TX pin to reach the control circuit shown in Figure 11.

The input pulse on TX is sampled during P2 of state 5 every machine cycle. A change on the input from high to low between samples will increment the counter. Each high and low state of the input pulse must thus be held constant for at least one machine cycle to ensure reliable counting. Since this takes 24 pulses, the maximum input frequency that can be accurately counted is the oscillator frequency divided by 24. for our 6 megahertz crystal. the calculation yields a maximum external frequency of 250 kilohertz.

External Memory

The system designer is not limited by the amount of internal RAM and ROM available on chip. Two separate external memory spaces are made available by the 16-bit PC and DPTR and by different control pins for enabling external ROM and RAM chips. Internal control circuitry accesses the correct physical memory, depending upon the machine cycle state and the opcode being executed.

There are several reasons for adding external memory, particularly program memory, when applying the 8051 in a system. When the project is in the prototype stage, the expense-in time and money-of having a masked internal ROM made for each program "try" is prohibitive. To alleviate this problem, the manufacturers make available an EPROM version, the 8751, which has 4K of on-chip EPROM that may be programmed and erased as needed as the program is developed. The resulting circuit board layout will be identical to one that uses a factory-programmed 8051. The only drawbacks to the 8751 are the specialized EPROM programmers that must be used to program the non-standard 40-pin part, and the limit of "only" 4096 bytes of program code.

The 8751 solution works well if the program will fit into 4K bytes. Unfortunately, many times, particularly if the program is written in a high-level language, the program size exceeds 4K bytes, and an external program memory is needed. Again, the manufac­turers provide a version for the job, the ROMless 8031. The (EA)’ pin is grounded when using the 8031, and all program code is contained in an external EPROM that may be as large as 64K bytes and that can be programmed using standard EPROM programmers.

External RAM, which is accessed by the DPTR, may also be needed when 128 bytes of internal data storage is not sufficient. External RAM, up to 64K bytes, may also be added to any chip in the 8051 family.

Connecting External Memory

Figure 8 shows the connections between an 8031 and an external memory configuration consisting of 16K bytes of EPROM and 8K bytes of static RAM. The 8051 accesses exter­nal RAM whenever certain program instructions are executed. External ROM is accessed whenever the EA(external access) pin is connected to ground or when the PC contains an address higher than the last address in the internal 4K bytes ROM (OFFFh). 8051 designs can thus use internal and external ROM automatically; the 8031 , having no internal ROM, must have (EA)’ grounded.

Figure 9 shows the timing associated with an external memory access cycle. Dur­ing any memory access cycle, port 0 is time multiplexed. That is, it first provides the lower byte of the 16-bit memory address, then acts as a bidirectional data bus to write or read a byte of memory data. Port 2 provides the high byte of the memory address during the entire memory read/write cycle.

The lower address byte from port 0 must be latched into an external register to save the byte. Address byte save is accomplished by the ALE clock pulse that provides the correct timing for the 373 type data latch. The port 0 pins then become free to serve as a data bus.

If the memory access is for a byte of program code in the ROM, the (PSEN)'(program store enable) pin will go low to enable the ROM to place a byte of program code on the data bus. If the access is for a RAM byte, the (WR)'(write) or (RD)'(read) pins will go low, enabling data to flow between the RAM and the data bus.

The ROM may be expanded to 64K by using a 27512 type EPROM and connecting the remaining port 2 upper address lines A14-A15 to the chip.

At this time the largest static RAMs available are 32K in size; RAM can be expanded to 64K by using two 32K RAMs that are connected through address A 14 of port 2. The

FIGURE 8 External Memory Connections

FIGURE9 External Memory Timing

FIGURE10     TCON and TMOD Function Registers

THE TIMER CONTROL (TCON) SPECIAL FUNCTION REGISTER

Continued

first 32K RAM (0000h- 7FFFh) can then be enabled when A 15 of port 2 is low, and the second 32K RAM (8000h-FFFFh) when A 15 is high, by using an inverter.

Note that the (WR)’ and (RD)’ signals are alternate uses for port 3 pins 16 and 17. Also, port 0 is used for the lower address byte and data; port 2 is used for upper address bits. The use of external memory consumes many of the port pins, leaving only port 1 and parts of port 3 for general I/O.

Input/Output Pins, Ports, and Circuits

One major feature of a microcontroller is the versatility built into the input/output (110) circuits that connect the 8051 to the outside world. As noted in Chapter I, microprocessor designs must add additional chips to interface with external circuitry; this ability is built into the microcontroller.

To be commercially viable, the 8051 had to incorporate as many functions as were technically and economically feasible. The main constraint that limits numerous functions is the number of pins available to the 8051 circuit designers. The DIP has 40 pins, and the success of the design in the marketplace was determined by the flexibility built into the use of these pins.

For this reason, 24 of the pins may each be used for one of two entirely different functions, yielding a total pin configuration of 64. The function a pin performs at any given instant depends, first, upon what is physically connected to it and, then, upon what software commands are used to "program" the pin. Both of these factors are under the complete control of the 805 J programmer and circuit designer.

Given this pin flexibility, the 8051 may be applied simply as a single component with 1/0 only, or it may be expanded to include additional memory, parallel ports, and serial data communication by using the alternate pin assignments. The key to programming an alternate pin function is the port pin circuitry shown in Figure 7.

Each port has a D-type output latch for each pin. The SFR for each port is made up of these eight latches, which can be addressed at the SFR address for that port. For in­stance, the eight latches for port 0 are addressed at location 80h; port 0 pin 3 is bit 2 of the P0 SFR. The port latches should not be confused with the port pins; the data on the latches does not have to be the same as that on the pins.

The two data paths are shown in Figure 7 by the circuits that read the latch or pin data using two entirely separate buffers. The top buffer is enabled when latch data is read, and the lower buffer, when the pin state is read. The status of each latch may be read from a latch buffer, while an input buffer is connected directly to each pin so that the pin status may be read independently of the latch state.

Different opcodes access the latch or pin states as appropriate. Port operations are determined by the manner in which the 8051 is connected to external circuitry.

Programmable port pins have completely different alternate functions. The configura­tion of the control circuitry between the output latch and the port pin determines the nature of any particular port pin function. An inspection of Figure 7 reveals that only port I cannot have alternate functions; ports 0, 2, and 3 can be programmed.

The ports are not capable of driving loads that require currents in the tens of milli­amperes (mA). As previously mentioned, the 8051 has many family members, and many are fabricated in varying technologies. An example range of logic-level currents, volt­ages, and total device power requirements is given in the following table:

These figures tell us that driving more than two LSTTL inputs degrades the noise immunity of the ports and that careful attention must be paid to buffering the ports when they must drive currents in excess of those listed. Again, one must refer to the manufac­turers’ data books when designing a "real" application.

Port 0

Port 0 pins may serve as inputs, outputs, or, when used together, as a bi-directional low ­order address and data bus for external memory. For example, when a pin is to be used as an input, a I must be written to the corresponding port 0 latch by the program, thus turn­ing both of the output transistors off, which in turn causes the pin to "float" in a high­ impedance state, and the pin is essentially connected to the input buffer .

When used as an output, the pin latches that are programmed to a 0 will turn on the lower FET, grounding the pin. All latches that are programmed to a I still float; thus, external pull up resistors will be needed to supply a logic high when using port 0 as an output.

When port 0 is used as an address bus to external memory, internal control signals switch the address lines to the gates of the Field Effect Transistories (FETs). A logic I on an address bit will turn the upper FET on and the lower FET off to provide a logic high at the pin. When the address bit is a zero, the lower FET is on and the upper FET off to provide a logic low at the pin. After the address has been formed and latched into external circuits by the Address Latch Enable (ALE) pulse, the bus is turned around to become a data bus. Port 0 now reads data from the external memory and must be configured as an input, so a logic I is automatically written by internal control logic to all port 0 latches.

Port 1

Port 1 pins have no dual functions. Therefore, the output latch is connected directly to the gate of the lower FET. which has an FET circuit labeled Internal FET Pullup as an active pullup load.

Used as an input. a I is written to the latch. turning the lower FET off; the pin and the input to the pin buffer are pulled high by the FET load. An external circuit can overcome the high impedance pullup and drive the pin low to input a 0 or leave the input high for a 1 .

If used as an output. the latches containing a 1 can drive the input of an external circuit high through the pullup. If a 0 is written to the latch. the lower FET is on. the pullup is off. and the pin can drive the input of the external circuit low.

To aid in speeding up switching times when the pin is used as an output. the internal FET pull up has another FET in parallel with it. The second FET is turned on for two oscillator time periods during a low-to-high transition on the pin. as shown in Figure 7. This arrangement provides a low impedance path to the positive voltage supply to help reduce rise times in charging any parasitic capacitances in the external circuitry.

Port 2

Port 2 may be used as an input/output port similar in operation to port 1. The alternate use of port 2 is to supply a high-order address byte in conjunction with the port 0 low-order byte to address external memory.

Port 2 pins are momentarily changed by the address control signals when supplying the high byte of a 16-bit address. Port 2 latches remain stable when external memory is addressed, as they do not have to be turned around (set to 1) for data input as is the case for port 0 .

Port 3

Port 3 is an input/output port similar to port 1 . The input and output functions can be programmed under the control of the P3 latches or under the control of various other spe­cial function registers. The port 3 alternate uses are shown in the following table:

Unlike ports 0 and 2. which can have external addressing functions and change all eight port bits when in alternate use. each pin of port 3 may be individually programmed to be used either as 110 or as one of the alternate functions.