microcontrollers -

Programming Techniques

Posted on October 22, 2014 by Farahat Leave a comment

Programming Techniques

1. Explain DAA instruction.

Ans. It stands for ‘decimal adjust accumulator’.

Execution of DAA instruction converts the content of the accumulator into two BCD

values. The system utilises the AC flag (not accessible by the programmer, but is used

internally for DAA operation) for this conversion by following the procedures stated below:

(a) If the lower order 4-bits (D3 – D0) of the accumulator is greater than 910 or if the AC flag is set, then this instruction (i.e., DAA) adds 0610 to the low-order 4-bits.

(b) If the higher order 4-bits (D7 – D4) of the accumulator is greater than 910 or if the CY flag is set, then this instruction (i.e., DAA) adds 6010 to the high-order 4-bits.

Examples follow to explain the above:

(i) Let ACC contains 34BCD. Add 19BCD to this

Here both higher order (0001) and lower order (0010) 4-bits are less than 910, but both AC and CY flags are set. Thus, DAA instruction execution will add 6610 to the result.

12 =	0	0	1	0	0	1
66 =	1	1	0	0	1	1
	1	1	1	1	0	0	= 78BCD

and since CY is already set, thus the answer is 178BCD.

2. What happens when HLT is executed in software?

Ans. All the buses go into the tri-state on execution of HLT instruction.

3. Write down the instructions that load H-L register pair by the contents of memory location 3500 H. Then move the contents to register C.

Ans. The corresponding instructions are

LXI H, 3500 H execution of this instruction loads H-L register pair with the contents of memory location 3500 H.

and MOV C, M execution of this instruction moves the contents of memory location 3500 H to register C.

4. Explain the two instructions (a) LDAX and (b) STAX

Ans. (a) The instruction LDAX indicates that the contents of the designated register pair point to a memory location and copies the contents of the memory location into the accumulator.

As an example, let D = 40 H, E = 50 H and memory location 4050 H = AB H. Then LDAX D transfers the contents of memory location 4050 H to the accumulator. Thus, after the execution of instruction, ACC = AB H

(b) STAX stands for ‘store accumulator indirect’. The contents of the accumulator are copied into the memory location specified by the contents of the register pair.

As an example, let D = 40 H and E = 50 H and ACC = AB H. Then STAX D stores the accumulator contents in the memory location 4050 H.

5. Explain the instructions (a) SHLD (b) LHLD.

4050 = AB H

Ans. (a) It stands for ‘Store H and L registers direct’. The instruction SHLD is followed by a 2-byte address. The content of L is stored in this address and the content of H is stored in the memory location that follows.

As an example, let H = 40 H and L = 50 H. Then execution of SHLD 6555 H stores 50 H in memory location 6555 H and 40 H is stored in 6556 H memory address.

(b) It stands for ‘Load H and L registers direct’.

It copies the contents of the memory location (that follows an LHLD instruction) into

L register and copies the contents of the next memory location in H register. The

contents of the two accessed memory locations remain unaltered.

As an example, let the memory location 3100 H and 3101 H contain 07 H and AF H

respectively. Then execution of LHLD 3100 H copies the content of 3100 H into L

and that of 3101 H into H register.

6. Memory location 3050 H is specified by HL pair and contains data FE H. Accumulator contains 14 H. Add the contents of memory location with accumulator. Store the result in 2050 H.

Ans. The program is written as follows:

LXIH, 3050 H ﬁ HL register pair points 3050 H memory location

ADD M ﬁ Add contents of 3050 H with accumulator

STA 2050 H ﬁ Result in accumulator is stored in 2050 H

Prior to execution of the program, memory location 3050 H is loaded with data

FE H and accumulator with 14 H.

7. What the instruction DCR M stands for?

Ans. Here the memory location M is pointed to by the content of HL register pair. On executing DCR M, the content of the memory location is decremented by 01. Thus, if the memory location, as pointed to by HL register pair is AB H, then DCR M makes the content of that memory location to be AA H.

8. What the instruction DAD H stands for?

Ans. On executing the DAD H, the content of HL register pair is multiplied by 2. As an example if

9. Explain the two instructions (a) RAR and (b) RRC. Ans. (a) RAR stands for ‘rotate accumulator right through carry’.

Let the accumulator content = 95 H and carry flag = 0. Then execution of RAR will

change the contents of CY flag and accumulator as follows:

Bit D0 is placed in CY flag and the bit in the CY flag is placed in D7.

(b) RRC stands for ‘rotate accumulator right’.

Let, accumulator content = 95 H and carry flag = 0. Then execution of RRC will change the contents of CY flag and accumulator as follows:

Bit D0 is placed in D7 as well as in CY flag.

10. Explain the two instructions (a) RAL (b) RLC.

Ans. (a) RAL stands for ‘rotate accumulator left through carry’.

Let accumulator content = 95 H and carry flag = 0. Then execution of RAL will change the contents of CY flag and accumulator as follows:

Here D7 is placed in CY flag and the bit in CY flag placed in D0

(b) RLC stands for ‘rotate accumulator left’.

Let accumulator content = 95 H and carry flag = 0. Then execution of RLC will change the contents of CY flag and accumulator as follows:

11. Explain the instruction SPHL.

Ans. It stands for ‘Copy H and L registers to the stack pointer’.

This instruction copies the contents of H and L registers into the stack pointer register. The content of H register goes to the high order address and the content of L register to the low order address of SP. H and L register contents remain unchanged.

Let H = 31 H and L = 32 H before the instruction is executed. Hence after its execution, it would be like as follows:

12. Explain the instruction PCHL.

Ans. It stands for ‘load program counter (PC) with HL contents’. The contents of H and L are copied into higher and lower order bytes of the PC. H and L register contents remain unchanged.

Let H = 31 H and L = 32 H before the instruction is executed. Hence after its execution, it would be as follows:

13. Write down the result of EX–OR operation on accumulator and register B. Assume ACC = 18 H and B = 27 H.

Ans. The instruction used for this operation is XRA B.

ACC

EX–OR

ﬁ

0 0

3F H

The result 3F H of EX–OR is stored in accumulator.

14. Consider the following:

Contents of H, L and SP registers are A0 H, B2 H and 3062 H. Memory locations 3062 H and 3063 H contain 52 H and 16 H respectively. Indicate the contents of these registers after XTHL operation.

Ans. XTHL stands for exchange H and L with top of stack.

Different Register contents before XTHL instruction

After XTHL instruction is carried out, the different register contents would be

15. Bring out the difference between arithmetic shift and logical shift.

Ans. An example, with a right shift, will be considered to bring out the difference between arithmetic shift and logical shift operations.

Let the accumulator content is

Then arithmetic right shift operation will make the contents of ACC as follows:

i.e., the sign bit of the original number is retained at the MSB place.

While logical right shift operation makes the ACC contents as follows:

i.e., the bits are shifted one bit position to the right.

16. Draw the flow chart and write down the program to add two numbers 16 H and D2 H. Store the result in memory location 3015 H.

Ans. The flowchart for the above would look as follows.

17. Write a program, along with flowchart, to find the 2’s complement of the number FF H, stored at memory location 2000 H. Store the result in memory location 3015 H.

Ans. The flowchart, along with the program, is shown below:

Memory location 2000 H contains data FF H.

18. Write down the program to add two sixteen bit numbers. Draw the corresponding flowchart also.

Ans. Let the two sixteen bit numbers are stored at memory locations 3500 H to 3503 H. The result of addition is to be stored at memory locations 3504 H and 3505 H. The flowchart and the program will look like as follow:

19. Ten 8-bit numbers are stored starting from memory location 2100 H. Add the numbers, store the result at 3500 H memory location and carry at 3501 H. Draw the flowchart also.

Ans. Initially, C register is stored with 09 H to take care of ten 8-bit data. Register D is initialised to 00 and stores the subsequent carry as addition is carried on. Final sum is stored at 3500 H while carry is stored at 3501 H.

The corresponding flowchart is also shown. Ten numbers of 8-bit data are stored starting from memory location 2100 H.

20. Ten 8-bit numbers are stored starting from memory location 3100 H. Find the greatest of the ten numbers and store it at memory location 3500 H.

Ans. Initially, D register is stored with 0A H—the number of data to be compared. The flowchart and the corresponding program are shown below:

21. Ten number 8-bit data are stored starting from memory location 2100 H. Transfer this entire block of data to memory location starting from 3100 H.

Ans. B register is used here as a counter which stores the number of data bytes to be transferred. The flowchart along with the program are shown below:

22. Set up a delay of 10 ms. Assume 3 MHz to be the microprocessor clock frequency.

Ans. Time delay is very easily generated by using a register (or a register pair— depending on the delay amount). Here the register pair BC is used to generate the delay with B loaded with 09 H and C with 03 H (calculations shown later). The flowchart and the program are shown side by side.

Calculations: A 3 MHz system clock corresponds to a time period of 0.3 ms. The

instructions MVI B, MVI C, DCX B and JNZ take 7, 7, 6 and 7 T-states respectively, of

which the two MVI instructions are outside the loop.

Time to execute MVI B and MVI C instructions.

= (7 + 7) × 0.3 ms

If the program loops n times, then time required for n loops

= time for 1 l.oop × n

= (6 + 7) × 0.3 × n

Thus 10 × 103 = (7 + 7) × 0.3 + (6 + 7) × 0.3 × n; ﬁ n ª 2307)10 = 0903)H

23. Generate a square wave of 50% duty cycle through the SOD pin of 8085. Ans. To generate a square wave, help of SIM instruction is taken. It reads like this

Thus, for a ‘1’ to come out of SOD pin, D7 and D6 of accumulator to be made 1 while for a ‘0’ to be taken out of SOD pin, D7 and D6 of accumulator to be made 0 and 1 respectively. In both the above cases, D5 to D0 (six bits in all) are to be put to 0. Thus the program reads like this:

Thus the above generates a square wave which is obtained through SOD pin of microprocessor, having time period of 2D (2 × delay time).

If a non 50% duty cycle is desired, then the two delays are made different, as desired.

24. A data byte is stored in memory location 4200 H. This eight bit data is to be taken out of SOD pin, bit wise.

Ans. The flowchart and the program are as follows:

8085 Interrupts

Posted on October 22, 2014 by Farahat Leave a comment

8085 Interrupts

1. Mention the interrupt pins of 8085.

Ans. There are five (5) interrupt pins of 8085—from pin 6 to pin 10. They represent TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR interrupts respectively. These five interrupts are ‘hardware’ interrupts.

2. Explain maskable and non-maskable interrupts.

Ans. An interrupt which can be disabled by software means, is called a maskable interrupt.

Thus an interrupt which cannot be masked is an unmaskable interrupt.

3. Which is the non maskable interrupt for 8085?

Ans. TRAP interrupt is the non-maskable interrupt for 8085. It means that if an interrupt comes via TRAP, 8085 will have to recognise the interrupt.

4. Do the interrupts of 8085 have priority?

Ans. Yes, the interrupts of 8085 have their priorities fixed—TRAP interrupt has the highest priority, followed by RST 7.5, RST 6.5, RST 5.5 and lastly INTR.

5. What is meant by priority of interrupts?

Ans. It means that if 8085 is interrupted by more than one interrupt at the same time, the one which is having highest priority will be serviced first, followed by the one(s) which is (are) having just next priority and so on.

For example, if 8085 is interrupted by RST 7.5, INTR and RST 5.5 at the same time,

then the sequence in which the interrupts are going to be serviced are as follows: RST

7.5, RST 5.5 and INTR respectively.

6. Mention the types of interrupts that

8085 supports.

Ans. 8085 supports two types of interrupts— hardware and software interrupts.

7. What are the software interrupts of 8085? Mention the instructions, their hex codes and the corresponding vector addresses.

Ans. 8085 has eight (8) software interrupts from RST 0 to RST 7. The instructions, hex codes and the vector locations are tabulated in Table 4.1:

Table 4.1: Vector addresses for software interrupts

Instruction	Corresponding HEX code	Vector addresses
RST 0	C7	0000H
RST 1	CF	0008H
RST 2	D7	0010H
RST 3	DF	0018H
RST 4	E7	0020H
RST 5	EF	0028H
RST 6	F7	0030H
RST 7	FF	0038H

8. How the vector address for a software interrupt is determined?

Ans. The vector address for a software interrupt is calculated as follows:

Vector address = interrupt number × 8

For example, the vector address for RST 5 is calculated as

5 × 8 = 40)10 = 28)H

Vector address for RST 5 is 0028H.

9. In what way INTR is different from the other four hardware interrupts? Ans. There are two differences, which are discussed below:

1. While INTR is not a vectored interrupt, the other four, viz., TRAP, RST 7.5, RST

6.5 and RST 5.5 are all vectored interrupts. Thus whenever an interrupt comes via any one of these four interrupts, the internal control circuit of 8085 produces a CALL to a predetermined vector location. At these vector locations the subroutines are written.

On the other hand, INTR receives the address of the subroutine from the external

device itself.

2. Whenever an interrupt occurs via TRAP, RST 7.5, RST 6.5 or RST 5.5, the corresponding returns address (existing in program counter) is auto-saved in STACK, but this is not so in case of INTR interrupt.

10. Indicate the nature of signals that will trigger TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR.

Ans. TRAP interrupt is both positive edge and level triggered, RST 7.5 is positive edge triggered while RST 6.5, RST 5.5 and INTR are all level triggered.

11. Why the TRAP input is edge and level sensitive?

Ans. TRAP input is edge and level sensitive to avoid false triggering caused by noise and transients.

12. Draw the TRAP interrupt circuit diagram and explain the same.

Ans.

The positive edge of the TRAP signal sets the D F/F, so that Q becomes 1. It thus enables the AND gate, but the AND gate will output a 1 for a sustained high level at the TRAP input. In that case the subroutine written at vector memory location 2400H corresponding to TRAP interrupt starts executing. 2400H is the starting address of an interrupt service routine for TRAP.

There are two ways to clear the TRAP interrupt:

1. When the microprocessor is resetted, then via the inverter, a high comes out of the OR gate, thereby clearing the D F/F, making Q = 0.

2. When a TRAP is acknowledged by the system, an internal TRAP ACKNOWLEDGE is generated thereby clearing the D F/F.

13. Discuss the INTR interrupt of 8085.

Ans. The following are the characteristics of INTR interrupt of 8085:

*It is a maskable interrupt

* It has lowest priority

* It is a non-vectored interrupt.

Sequentially, the following occurs when INTR signal goes high:

1. 8085 checks the status of INTR signal during execution of each instruction.

2. If INTR signal remains high till the completion of an instruction, then 8085 sends

out an active low interrupt acknowledge (INTA) signal.

3. When INTA signal goes low, external logic places an instruction OPCODE on the

data bus.

4. On receiving the instruction, 8085 saves the address of next instruction (which would have otherwise been executed) in the STACK and starts executing the ISS (interrupt service subroutine).

14. Draw the diagram that outputs RST 3 instruction opcode on acknowledging the interrupt.

Ans. The diagram is shown below:

When an INTR is acknowledged by the microprocessor, it outputs a low INTA . Thus

an RST 3 is gated onto the system bus. The processor then first saves the PC in the STACK and branches to the location 0018H. At this address, the ISS begins and ends with a RET instruction. On encountering RET instruction in the last line of the ISS, the return address saved in the stack is restored in the PC so that normal processing in the main program (at the address which was left off when the program branched to ISS) begins.

15. What is to be done if a particular part of a program is not to be interrupted by RST 7.5, RST 6.5, RST 5.5 and INTR?

Ans. Two software instructions—EI and DI are used at the beginning and end of the particular portion of the program respectively. The scheme is shown schematically as follows:

16. Explain the software instructions EI and DI.

Ans. The EI instruction sets the interrupt enable flip-flop, thereby enabling RST 7.5, RST 6.5, RST 5.5 and INTR interrupts.

The DI instruction resets the interrupt enable flip-flop, thereby disabling RST 7.5, RST 6.5, RST 5.5 and INTR interrupts.

17. When returning back to the main program from Interrupt Service Subroutine (ISS), the software instruction EI is inserted at the end of the ISS. Why?

Ans. When an interrupt (either via RST 7.5, RST 6.5, RST 5.5, INTR) is acknowledged by the microprocessor, ‘any interrupt acknowledge’ signal resets the interrupt enable F/F. It thus disables RST 7.5, RST 6.5, RST 5.5 and INTR interrupts. Thus any future interrupt coming via RST 7.5, RST 6.5, RST 5.5 or INTR will not be acknowledged unless the software instruction EI is inserted which thereby sets the interrupt enable F/F.

18. Mention the ways in which the three interrupts RST 7.5, RST 6.5 and RST 5.5 are disabled?

Ans. The three interrupts can be disabled in the following manner:

*Software instruction DI

* RESET IN signal

*Any interrupt acknowledge signal.

19. Draw the SIM instruction format and discuss.

Ans. The SIM instruction format is shown below:

D7 and D6 bits are utilised for serial outputting of data from accumulator. D5 bit is a don’t care bit, while bits D4–D0 are used for interrupt control.

D4 bit can clear the D F/F associated with RST 7.5.

D3 bit is mask set enable (MSE) bit, while bits D2–D0 are the masking bits

corresponding to RST 7.5, RST 6.5 and RST 5.5 respectively.

None of the flags are affected by SIM instruction.

By employing SIM instruction, the three interrupts RST 7.5, RST 6.5 and RST 5.5 can be masked or unmasked. For masking any one of these three interrupts, MSE (i.e., bit D3) bit must be 1.

For example let RST 7.5 is to be masked (disabled), while RST 6.5 and RST 5.5 are

to be unmasked (enabled), then the content of the bits of the SIM instruction will be like 0000 1100 = 0CH

For this to be effective the following two instructions are written,

MVI A, 0CH SIM

Execution of SIM instruction allows copying of the contents of the accumulator into

the interrupt masks.

20. Show the RIM instruction format and discuss the same. Ans. RIM stands for ‘Read interrupt mask’ and its format is as follows:

When RIM instruction is executed in software, the status of SID, pending interrupts and interrupt masks are loaded into the accumulator. Thus their status can be monitored. It may so happen that when one interrupt is being serviced, other interrupt(s) may occur. The status of these pending interrupts can be monitored by the RIM instruction. None of the flags are affected by RIM instruction.

21. Write a program which will call the interrupt service subroutine (at 3C00H) corresponding to RST 7.5 if it is pending. Let the ACC content is 20 H on executing the RIM instruction.

Ans. The program for the above will be as hereunder:

22. Write a program which will call the subroutine (say named ‘SR’) if RST 6.5 is masked. Let content of ACC is 20 H on executing the RIM instruction.

Ans. RST 6.5 is masked if bit M¢6.5 (D1 bit of RIM) is a 1 and also D3 bit (i.e., IE) is 1 The program for the above will be as hereunder:

23. For what purpose TRAP interrupt is normally used?

Ans. TRAP interrupt is a non-maskable one i.e., if an interrupt comes via the TRAP input, the system will have to acknowledge that. That is why it is used for vital purposes which require immediate attention like power failure.

If the microprocessor based system loses power, the filter capacitors hold the supply voltage for several mili seconds.

During this time, data in the RAM can be written in a disk or E2PROM for future

usage.

24. Draw the interrupt circuit diagram for 8085 and explain.

Ans. Figure 4.6 is the interrupt circuit diagram of 8085. It shows the five hardware interrupts TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR along with the software interrupts RST n: n = 0 to 7.

Trap is both edge and level sensitive interrupt. A short pulse should be applied at the

trap input, but the pulse width must be greater than a normal noise pulse width and also long enough for the µP to complete its current instruction. The trap input must come down to low level for it to be recognised for the second time by the system. It is having highest priority.

Next highest priority interrupt is RST 7.5 which responds to the positive edge

(low to high transition) of a pulse. Like trap, it also has a D F/F whose output becomes 1 on accepting the RST 7.5 input, but final call to vector location 3C00H is reached only if RST 7.5 remains unmasked and the program has an EI instruction inserted already. These are evident from the circuit. If R 7.5 (bit D4 of SIM instruction) is 1, then RST 7.5 instruction will be overlooked i.e., it can override any RST 7.5 interrupt.

Like RST 7.5, final call locations 3400H and 2C00H corresponding to interrupts at RST 6.5 and RST 5.5 are reached only if the two interrupts remain unmasked and the software instruction EI is inserted.

The three interrupts RST 7.5, RST 6.5 and RST 5.5 are disabled once the system accepts an interrupt input via any one of these pins—this is because of the generation of ‘any interrupt acknowledge’ signal which disables them.

Any of the software RST instructions (RST n : n = 0 to 7) can be utilised by using

INTR instruction and hardware logic. RST instructions are utilised in breakpoint service routine to check register(s) or memory contents at any point in the program.

25. The process of interrupt is asynchronous in nature. Why?

Ans. Interrupts may come and be acknowledged (provided masking of any interrupt is not done) by the microprocessor without any reference to the system clock. That is why interrupts are asynchronous in nature.

26. In how many categories can ‘interrupt requests’ be classified?

Ans. The ‘interrupt requests’ can be classified into two categories—maskable interrupt and non-maskable interrupt.

A maskable interrupt can either be ignored or delayed as per the needs of the system

while a non-maskable interrupt has to be acknowledged.

27. When the interrupt pins of 8085 are checked by the system?

Ans. Microprocessor checks (samples) interrupt pins one cycle before the completion of an instruction cycle, on the falling edge of the clock pulse. An interrupt occurring at least 160 ns (150 ns for 8085A-2, since it is faster in operation) before the sampling time is treated as a valid interrupt.

28. Is there a minimum pulse width required for the INTR signal?

Ans. Microprocessor issues a low INTA signal as an acknowledgement on receiving an INTR interrupt input signal. A CALL instruction is then issued so that the program branches to Interrupt Service Subroutine (ISS). Now the CALL requires 18 T-states to complete. Hence the INTR pulse must remain high for at least 17.5 T-states. If 8085 is operated at 3 MHz clock frequency, then the INTR pulse must remain high for at least 5.8 mS.

29. Can the microprocessor be interrupted before completion of existing Interrupt Service Subroutine (ISS)?

Ans. Yes, the microprocessor can be interrupted before the completion of the existing ISS.

Let after acknowledging the INTR, the microprocessor is in the ISS executing instructions one by one. Now, for a given situation, if the interrupt system is enabled (by inserting an EI instruction) just after entering the ISS, the system can be interrupted again while it is in the first ISS.

If an interrupt service subroutine be interrupted again then this is called ‘nested interrupt’.

30. Bring out one basic difference between SIM and DI instructions.

Ans. While by using SIM instruction any combinations or all of RST 7.5, RST 6.5 and RST 5.5 can be disabled, on the other hand DI disables RST 7.5, RST 6.5, RST 5.5 and in addition INTR interrupt also.

31. What is RIM instruction and what does it do?

Ans. The instruction RIM stands for Read Interrupt Mask. By executing this instruction in software, it is possible to know the status of interrupt mask, pending interrupt(s), and serial input.

32. In an interrupt driven system, EI instruction should be incorporated at the beginning of the program. Why?

Ans. A program, written by a programmer in the RAM location, is started first by system reset and loading the PC with the starting address of the program.

Now, with a system reset, all maskable interrupts are disabled. Hence, an EI

instruction must be put in at the beginning of the program so that the maskable interrupts, which should remain unmasked in a program, remain so.

33. How the system can handle multiple interrupts?

Ans. Multiple interrupts can be handled if a separate interrupt is allocated to each peripheral.

The programmable interrupt controller IC 8259 can also be used to handle multiple interrupts when they are interfaced through INTR.

34. When an interrupt is acknowledged, maskable interrupts are automatically disabled. Why?

Ans. This is done so that the interrupt service subroutine (ISS) to which the program has entered on receiving the interrupt, has a chance to complete its own task.

35. What is meant by ‘nested interrupts’? What care must be taken while handling nested interrupts?

Ans. Interrupts occurring within interrupts are called ‘nested interrupts’.

While handling nested interrupts, care must be taken to see that the stack does not grow to such an extent as to foul the main program—in that case the system program fails.

36. ‘A RIM instruction should be performed immediately after TRAP occurs’—Why?

Ans. This is so as to enable the pre-TRAP interrupt status to be restored with the implementation of a SIM instruction.

37. What does the D4 bit of SIM do?

Ans. Bit D4 of SIM is R 7.5 which is connected to RST 7.5 F/F via a OR gate. If D4 of SIM is made a 1, then it resets RST 7.5 F/F. This thus can be used to override RST 7.5 without servicing it.

38. Comment on the TRAP input of 8085.

Ans. Trap input is both edge and level sensitive. It is a narrow pulse, but the pulse width should be more than normal noise pulse width. This is done so that noise cannot affect the TRAP input with a false triggering. Again the pulse width should be such that the TRAP input which is directly connected to the gate stays high till the completion of current instruction by the mP. In that case, only the program gets diverted to vector call location 2400 H.

TRAP cannot respond for a second time until the first TRAP goes through a high to low transition.

TRAP interrupt, once acknowledged, goes to 2400 H vector location without any external hardware or EI instruction, as is the case for other interrupt signals to be acknowledged.

39. Discuss about the triggering levels of RST 7.5, RST 6.5 and RST 5.5.

Ans. RST 7.5 is positive edge sensitive and responds to a short trigger pulse. The interrupt that comes via RST 7.5 is stored in a D F/F, internal to mP. The final vector call location 3C00 H is invoked only if RST 7.5 remains unmasked via SIM and software instruction EI is inserted in the program.

RST 6.5 and 5.5 respond to high level (i.e., level sensitive) at their input pins—thus these two pins must remain high until microprocessor completes the execution of the current instruction.

40. Discuss the utility of RST software instruction.

Ans. For an RST instruction (RST n, n : 0 to 7) to become effective, external hardware is necessary, along with INTR interrupt instruction.

When debugging is required in a program to know the register(s) or memory contents, breakpoints are inserted via RST instruction.

A breakpoint is an RST instruction inserted in a program. When an RST instruction is recognised, the program control is transferred to the corresponding RST vector location. From this vector location, it is again transferred to the breakpoint service routine so that programmer can check the contents of any register or memory content on pressing specified key(s). After testing, the routine returns to the breakpoint in the main program.

Thus RST instructions can be inserted within a program to examine the register/

memory content as per the requirement.

41. Under what condition, an RST instruction is going to be recognised?

Ans. Any RST instruction is recognised only if the EI instruction is incorporated via software.

42. Can the ‘TRAP’ interrupt be disabled by a combination of hardware and software?

Ans. Yes, it can be disabled by SIM instruction and hardware, as shown in Fig. 4.7.

The following two instructions are executed.

MVIA, 40 H

SIM

It ensures that a ‘0’ logic comes out via SOD pin (pin 4) of 8085. This is then ANDed with TRAP input.

Thus pin 6 (TRAP) always remains at ‘0’ logic and hence TRAP input is disabled or ‘MASKED’.

43. Level wise, how the interrupts can be classified? Distinguish them.

Ans. Level wise, interrupts can be classified as

1 single level interrupts

2 multi level interrupts

Their distinguishing features are shown below:

Single level interrupt

Multi level interrupt

1. Interrupts are fed via a single pin

of microprocessor (like INTR of 8085)

2. CPU polls the I/O devices to identify the interrupting device.

3. Slower because of sl. no. 2.

1. Interrupts are fed via different pins of microprocessor (like RST 7.5, RST 6.5 etc), each interrupt requiring a separate pin of microprocessor.

2. Since each interrupt pin corresponds to a single I/O device, polling is not necessary.

3. Faster because of sl. no. 2.

Instruction Types and Timing Diagrams

Posted on October 22, 2014 by Farahat Leave a comment

Instruction Types and Timing Diagrams

1. What is an instruction?

Ans. An instruction is a command given to the microcomputer to perform a specific task or function on a given data.

2. What is meant by instruction set?

Ans. An instruction set is a collection of instructions that the microprocessor is designed to perform.

3. In how many categories the instructions of 8085 be classified? Ans. Functionally, the instructions can be classified into five groups:

*data transfer (copy) group

*arithmetic group

*logical group

* branch group

*stack, I/O and machine control group.

4. What are the different types of data transfer operations possible? Ans. The different types of data transfer operations possible are cited below:

* Between two registers.

* Between a register and a memory location.

*A data byte can be transferred between a register and a memory location.

* Between an I/O device and the accumulator.

*Between a register pair and the stack.

The term ‘data transfer’ is a misnomer—actually data is not transferred, but copied from source to destination.

5. Mention the different types of operations possible with arithmetic, logical, branch and machine control operations.

Ans. The arithmetic operations possible are addition, subtraction, increment and decrement.

The logical operations include AND, OR, EXOR, compare, complement, while branch

operations are Jump, Call, Return and Restart instructions.

The machine control operations are Halt, Interrupt and NOP (no operation).

6. What are the different instruction word sizes in 8085? Ans. The instruction word sizes are of the following types:

Instruction Types and Timing Diagrams 33

z 1-byte instruction z 2-byte instruction z 3-byte instruction.

7. What an instruction essentially consists of?

Ans. An instruction comprises of an operation code (called ‘opcode’) and the address of the data (called ‘operand’), on which the opcode operates. This is the structure on which an instruction is based. The opcode specifies the nature of the task to be performed by an instruction. Symbolically, an instruction looks like

8. Give one example each of 1-byte, 2-byte and 3-byte instructions.

Ans. The examples are given below:

* 1-byte instruction : ADD B

* 2-byte instruction : MVIC, 07

* 3-byte instruction : LDA 4400

9. What is meant by ‘addressing mode’? Mention the different addressing modes.

Ans. Each instruction indicates an operation to be performed on certain data. There are various methods to specify the data for the instructions, known as ‘addressing modes’.

For 8085 microprocessor, there are five addressing modes. These are:

*Direct addressing

* Register addressing

* Register indirect addressing

* Immediate addressing

*Implicit addressing.

10. Give one example each of the five types of addressing modes. Ans. The examples for each type of addressing mode are given below:

(a) Direct Addressing: In this mode, the operand is specified within the instruction itself.

Examples of this type are:

LDA 4000H, STA 5513H, etc.

IN/OUT instructions (like IN PORT C, OUT PORT B, etc.) also falls under this category.

(b) Register Addressing: In this mode of addressing, the operand are in the general purpose registers.

Examples are: MOV A, B ; ADD D, etc.

(c) Register Indirect Addressing: MOV A, M; ADD M are examples of this mode of addressing. These instructions utilise 1-byte. In this mode, instead of specifying a register, a register pair is specified to accommodate the 16-bit address of the operand.

(d) Immediate Addressing: MVI A, 07; ADI 0F are examples of Immediate Addressing mode.

The operand is specified in the instruction in this mode. Here, the operand address is not specified.

(e) Implicit Addressing: In this mode of addressing, the operand is fully absent. Examples are RAR, RAL, CMA, etc.

11. Let at the program memory location 4080, the instruction MOV B, A (opcode 47H) is stored while the accumulator content is FFH. Illustrate the execution of this instruction by timing diagram.

Ans. Since the program counter sequences the execution of instructions, it is assumed that

the PC holds the address 4080H. While the system one after another.

1. The CPU places the address 4080H (residing in PC) on the address bus—40H on the high

CLK A 1 T2 T3 T4 order bus A15 – A8 and 80H on the low order bus AD7 – AD0.

2. The CPU raises the ALE signal to go high—the H to L transition of ALE at the end of the

first T state demultiplexes the low order bus.

3. The CPU identifies the nature of the machine cycle by means of the three status IO/M

signals IO/ M , S0 and S1.

IO/ = 0, S1 = 1, S₀ = 1

4. In T2, memory is enabled by the signal.

The content of PC i.e., 47H is placed on the data bus. PC is incremented to 4081H.

5. In T₃, CPU reads 47_H and places it in the instruction register.

6. In T4, CPU decodes the instruction, places FFH (accumulator content) in the temporary register and then transfers it to register B. Figure 3.1 shows the execution of the above. It consists of 4T states.

The 8085 Microprocessor

Posted on October 21, 2014 by Farahat Leave a comment

The 8085 Microprocessor

1. Draw the pin configuration and functional pin diagram of μP 8085. Ans. The pin configuration and functional pin diagram of μP 8085 are shown below:

2. In how many groups can the signals of 8085 be classified?

Ans. The signals of 8085 can be classified into seven groups according to their functions. These are:

(1) Power supply and frequency signals (2) Data and Address buses (3) Control bus

(4) Interrupt signals (5) Serial I/O signals (6) DMA signals (7) Reset signals.

3. Draw the architecture of 8085 and mention its various functional blocks. Ans. The architecture of 8085 is shown below:

Fig. 2.2: Architecture of 8085

The various functional blocks of 8085 are as follows:

1.Registers

2.Arithmetic logic unit

3.Address buffer

4.Incrementer/decrementer address latch

5.Interrupt control

6. Serial I/O control

7.Timing and control circuitry

8.Instructions decoder and machine cycle encoder.

4. What is the technology used in the manufacture of 8085?

Ans. It is an NMOS device having around 6200 transistors contained in a 40 pin DIP package.

5. What is meant by the statement that 8085 is a 8-bit microprocessor?

Ans. A microprocessor which has n data lines is called an n-bit microprocessor i.e., the width of the data bus determines the size of the microprocessor. Hence, an 8-bit microprocessor like 8085 can handle 8-bits of data at a time.

6. What is the operating frequency of 8085?

Ans. 8085 operates at a frequency of 3 MHz, and the minimum frequency of operation is 500 kHz.

The version 8085 A-2 operates at a maximum frequency of 5 MHz.

7. Draw the block diagram of the built-in clock generator of 8085.

Ans. The built-in clock generator of 8085, in block schematic, is shown below:

The internal built-in clock generator, LC or RC tuned circuits, piezo-electric crystal or external clock source acts as an input to generate the clock. The T F/F, shown in Fig.

2.3 divides the input frequency by 2. Thus the output frequency of 8085 (obtained from pin 37) is half the input frequency.

8. What is the purpose of CLK signal of 8085?

Ans. The CLK (out) signal obtained from pin 37 of 8085 is used for synchronizing external devices.

9. Draw the different clock circuits which can be connected to pins 1 and 2 of 8085.

Ans. The different external clock circuits which can be connected to pins 1 and 2 of 8085 are shown below in Fig. 2.4:

Fig. 2.4: The different external clock circuits

The output frequency obtained from pin 37 of Fig. 2.4(b) is more stable than the RC circuit of Fig. 2.4(a).

10. What are the widths of data bus (DB) and address bus (AB) of 8085?

Ans. The width of DB and AB of 8085 are 8-bits (1 byte) and 16-bits (2 bytes) respectively.

11. What is the distinguishing feature of DB and AB?

Ans. While the data bus is bidirectional in nature, the address bus is unidirectional.

Since the mP can input or output data from within it, hence DB is bidirectional. Again the microprocessor addresses/communicates with peripheral ICs through the address bus, hence it is unidirectional, the address comes out via the AB of mP.

12. The address capability of 8085 is 64 KB. Explain.

Ans. Microprocessor 8085 communicates via its address bus of 2-bytes width – the lower byte AD0 – AD7 (pins 12-19) and upper byte D8 – D15 (pins 21–28). Thus it can address a maximum of 216 different address locations. Again each address (memory location) can hold 1 byte of data/instruction. Hence the maximum address capability of 8085 is

= 216 × 1 Byte

= 65, 536 × 1 Byte

= 64 KB (where 1 K = 1024 bytes)

13. Does 8085 have serial I/O control?

Ans. 8085 has serial I/O control via its SOD and SID pins (pins 4 and 5) which allows it to communicate serially with external devices.

14. How many instructions 8085 can support? Ans. 8085 supports 74 different instructions.

15. Mention the addressing modes of 8085.

Ans. 8085 has the following addressing modes: Immediate, Register, Direct, Indirect and Implied.

16. What jobs ALU of 8085 can perform?

Ans. The Arithmetic Logic Unit (ALU) of 8085 can perform the following jobs:

1.8-bit binary addition with or without carry.

2.16-bit binary addition.

3. 2-digit BCD addition.

4. 8-bit binary subtraction with or without borrow.

5. 8-bit logical OR, AND, EXOR, complement (NOT function).

6.bit shift operation.

17. How many hardware interrupts 8085 supports?

Ans. It supports five (5) hardware interrupts—TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR.

18. How many I/O ports can 8085 access?

Ans. It provides 8-bit I/O addresses. Thus it can access 28 = 256 I/O ports.

19. Why the lower byte address bus (A0 – A7) and data bus (D0 – D7) are multiplexed? Ans. This is done to reduce the number of pins of 8085, which otherwise would have been a

48 pin chip. But because of multiplexing, external hardware is required to demultiplex

the lower byte address cum data bus.

20. List the various registers of 8085.

Ans. The various registers of 8085, their respective quantities and capacities are tabulated below:

21. Describe the accumulator register of 8085.

Ans. This 8-bit register is the most important one amongst all the registers of 8085. Any data input/output to/from the microprocessor takes place via the accumulator (register). It is generally used for temporary storage of data and for the placement of final result of arithmetic/logical operations.

Accumulator (ACC or A) register is extensively used for arithmetic, logical, store and rotate operations.

22. What are the temporary registers of 8085?

Ans. The temporary registers of 8085 are temporary data register and W and Z registers. These registers are not available to the programmer, but 8085 uses them internally to hold temporary data during execution of some instructions.

23. Describe W and Z registers of 8085.

Ans. W and Z are two 8-bit temporary registers, used to hold 8-bit data/address during execution of some instructions.

CALL-RET instructions are used in subroutine operations. On getting a CALL in the main program, the current program counter content is pushed into the stack and loads the PC with the first memory location of the subroutine. The address of the first memory location of the subroutine is temporarily stored in W and Z registers.

Again, XCHG instruction exchanges the contents H and L with D and E respectively. W and Z registers are used for temporary storage of such data.

24. Describe the temporary data register of 8085.

Ans. The temporary data register of 8085 is an 8-bit register, which is not available to the programmer, but is used internally for execution of most of the arithmetic and logical operations.

ADD D instruction adds the contents of accumulator with the content of D. The content of D is temporarily brought into the temporary data register. Thus the two inputs to the ALU are—one from the accumulator and the other from the temporary data register. The result is stored in the accumulator.

25. Describe the general purpose registers of 8085?

Ans. The general purpose registers of 8085 are: B, C, D, E, H and L. They are all 8-bit registers but can also be used as 16-bit register pairs—BC, DE and HL. These registers are also known as scratch pad registers.

26. In what other way HL pair can be used?

Ans. HL register pair can be used as a data pointer or memory pointer.

27. Mention the utility of the general purpose registers.

Ans. General purpose registers store temporary data during program execution, which can also be stored in different accessible memory locations. But storing temporary data in memory requires bus access—hence more time is needed to store. Thus it is always advisable to store data in general purpose registers.

The more the number of general purpose registers, the more is flexibility in programming—so a microprocessor having more such registers is always advantageous.

28. Which are the sixteen bit registers of 8085.

Ans. 8085 has three (3) sixteen bit registers—Program Counter (PC), Stack Pointer (SP) and Incrementer/Decrementer address latch register.

29. Discuss the two registers program counter and stack pointer.

Ans. Program counter (PC) is a sixteen bit register which contains the address of the instruction to be executed just next. PC acts as a address pointer (also known as memory pointer) to the next instruction. As the processor executes instructions one after another, the PC is incremented—the number by which

the PC increments depends on the nature of the instruction. For example, for a 1-byte instruction, PC is incremented by one, while for a 3-byte instruction, the processor increments PC by three address locations.

Stack pointer (SP) is a sixteen bit register which points to the ‘stack’. The stack is an area in the R/W memory where temporary data or return addresses (in cases of subroutine CALL) are stored. Stack is a auto- decrement facility provided in the system. The stack top is initialised by the SP by using the instruction LXI SP, memory address.

In the memory map, the program should Fig. 2.5: Auto-increment and be written at one end and stack should be auto-decrement facility for PC initialised at the other end of the map—this is and SP respectively done to avoid crashing of program. If sufficient

gap is not maintained between program memory location and stack, then when the stack gets filled up by PUSH or subroutine calls, the stack top may run into the memory area where program has been written. This is shown in Fig. 2.5.

30. Describe the instruction register of 8085.

Ans. Program written by the programmer resides in the R/W memory. When an instruction is being executed by the system, the opcode of the instruction is fetched from the memory and stored in the instruction register. The opcode is loaded into the instruction register during opcode fetch cycle. It is then sent to the instruction decoder.

31. Describe the (status) flag register of 8085.

Ans. It is an 8-bit register in which five bit positions contain the status of five condition flags which are Zero (Z), Sign (S), Carry (CY), Parity (P) and Auxiliary carry (AC). Each of these five flags is a 1 bit F/F. The flag register format is shown in Fig. 2.6:

* Sign (S) flag: – If the MSB of the result of an operation is 1, this flag is set, otherwise it is reset.

* Zero (Z) flag:– If the result of an instruction is zero, this flag is set, otherwise reset.

* Auxiliary Carry (AC ) flag:– If there is a carry out of bit 3 and into bit 4 resulting from the execution of an arithmetic operation, it is set otherwise reset.

This flag is used for BCD operation and is not available to the programmer to change the sequence of an instruction.

* Carry (CY) flag:– If an instruction results in a carry (for addition operation) or borrow (for subtraction or comparison) out of bit D7, then this flag is set, otherwise reset.

* Parity (P) flag:– This flag is set when the result of an operation contains an even number of 1’s and is reset otherwise.

32. State the characteristics of the flag register. Ans. The following are the characteristics of flag register:

z It is an 8-bit register.

z It contains five flags—each of one bit.

z The flag register can’t be written into.

33. What is the purpose of incrementer/decrementer address latch register?

Ans. This 16-bit register increments/decrements the contents of PC or SP when instructions related to them are executed.

34. Mention the blocks on which ALU operates?

Ans. The ALU functions as a part which includes arithmetic logic group of circuits. This includes accumulator, flags F/Fs and temporary register blocks.

35. What is the function of the internal data bus?

Ans. The width of the internal data bus is 8-bit and carries instructions/data between the CPU registers. This is totally separate from the external data bus which is connected to memory chips, I/O, etc.

The internal and external data bus are connected together by a logic called a bidirectional bus (transreceiver).

36. Describe in brief the timing and control circuitry of 8085.

Ans. The T&C section is a part of CPU and generates timing and control signals for execution of instructions. This section includes Clock signals, Control signals, Status signals, DMA signals as also the Reset section. This section controls fetching and decoding operations. It also generates appropriate control signals for instruction execution as also the signals required to interface external devices.

37. Mention the following:

(a) Control and Status signals

(b) Interrupt signals

(d) DMA signals

(e) Reset signals.

Ans. The control and status signals are ALE, RD , WR , IO/M , S0, S1 and READY.

The interrupt signals are TRAP, RST 7.5, RST 6.5, RST 5.5, INTR. INTA is an

interrupt acknowledgement signal indicating that the processor has acknowledged an

INTR interrupt.

Serial I/O signals are SID and SOD

DMA signals are HOLD and HLDA

Reset signals are RESET IN and RESET OUT.

38. What is the function of ALE and how does it function?

Ans. Pin 30 of 8085 is the ALE pin which stands for ‘Address Latch Enable’. ALE signal is used to demultiplex the lower order address bus (AD0 – AD7).

Pins 12 to 19 of 8085 are AD0 – AD7 which is the multiplexed address-data bus. Multiplexing is done to reduce the number of pins of 8085.

Lower byte of address (A0 – A7) are available from AD0 – AD7 (pins 12 to 19) during T1 of machine cycle. But the lower byte of address (A0 – A7), along with the upper byte A8 – A15 (pins 21 to 28) must be available during T2 and rest of the machine cycle to access memory location or I/O ports.

Now ALE signal goes high at the beginning of T1 of each machine cycle and goes low at the end of T1 and remains low during the rest of the machine cycle. This high to low transition of ALE signal at the end of T1 is used to latch the lower order address byte (A0 – A7) by the latch IC 74LS373, so that the lower byte A0 – A7 is continued to be available till the end of the machine cycle. The situation is explained in the following figure:

Fig. 2.7: Lower byte of address latching achieved by the H to L transition of ALE signal, which occurs at the end of T1 of each machine cycle

39. Explain the function of the two DMA signals HOLD and HLDA.

Ans. DMA mode of data transfer is fastest and pins 39 and 38 (HOLD and HLDA) become active only in this mode.

When DMA is required, the DMA controller IC (8257) sends a 1 to pin 39 of 8085. At the end of the current instruction cycle of the microprocessor it issues a 1 to pin 38 of the controller. After this the bus control is totally taken over by the controller.

When 8085 is active and 8257 is idle, then the former is MASTER and the latter is SLAVE, while the roles of 8085 and 8257 are reversed when 8085 is idle and 8257 becomes active.

40. Discuss the three signals IO/ M , S0 and S1.

Ans. IO/ M signal indicates whether I/O or memory operation is being carried out. A high on this signal indicates I/O operation while a low indicates memory operation. S0 and S1 indicate the type of machine cycle in progress.

41. What happens when RESET IN signal goes low?

Ans. RESET IN is an input signal which is active when its status is low. When this pin is

low, the following occurs:

z The program counter is set to zero (0000H).

z Interrupt enable and HLDA F/Fs are resetted.

z All the buses are tri-stated.

z Internal registers of 8085 are affected in a random manner.

42. Is there any minimum time required for the effective RESET IN signal?

Ans. For proper resetting to take place, the reset signal RESET IN must be held low for at

least 3 clock cycles.

43. Indicate the function of RESET OUT signal.

Ans. When this signal is high, the processor is being reset. This signal is synchronised to the processor clock and is used to reset other devices which need resetting.

44. Write the advantages/disadvantages of having more number of general purpose registers in a microprocessor.

Ans. Writing of a program becomes more convenient and flexible by having more number of general purpose registers.

But there are certain disadvantages of having more GPRs. These are as follows:

The more the number of GPRs in a microprocessor, more number of bits would be required to identify individual registers. This would reduce the number of operations that can be provided by the microprocessor.

In programs involving subroutine CALL, if more GPRs are involved, then their

status are to be saved in stack and on return from the subroutine, they are to be restored

from the stack. This will thus put considerable overhead on the microprocessor.

If more number of GPRs are used in a microprocessor, considerable area of the chip

is used up in accommodating the GPRs. Thus there may be some problem in

implementing other functions on the chip.

45. Draw the lower and higher order address bus during the machine cycles.

Ans. The lower byte of address (AD0 – AD7) is available on the multiplexed address/data bus during T1 state of each machine cycle, except during the bus idle machine cycle, shown in Fig. 2.8.

The higher byte of address (A8 – A15) is available during T1 to T3 states of each machine cycle, except during the bus idle machine cycle, shown in Fig. 2.9.

46. Draw the appearance of data in the read and write machine cycles.

Ans. Data transfer from memory or I/O device to microprocessor or the reverse takes place during T2 and T3 states of the machine cycles.

In the read machine cycle, data appears at the beginning of T3 state, whereas in the write machine cycle, it appears at the beginning of T2, shown in Fig. 2.10.

Fig. 2.10: Data bus

47. Draw the status signals during opcode fetch and memory read machine cycles.

Ans. The status signals are IO/ M , S0 and S1. Their conditions indicate the type of machine cycle that the system is currently passing through. These three status signals remain active right from the beginning till the end of each machine cycle, shown in Fig. 2.11.

48. Show the RD and WR signals during the Read cycle and Write cycle.

Ans. When RD is active, microprocessor reads data from either memory or I/O device while

when WR is active, it writes data into either memory or I/O device.

Data transfer (reading/writing) takes place during T2 and T3 states of read cycle or write cycle and is shown in Fig. 2.12.

49. Indicate the different machine cycles of 8085.

Ans. 8085 has seven different machine cycles. These are:

(1) Opcode Fetch (2) Memory Read (3) Memory Write (4) I/O Read (5) I/O Write

(6) Interrupt Acknowledge (7) Bus Idle.

50. Draw the Opcode Fetch machine cycle of 8085 and discuss.

Ans. The first machine cycle of every instruction is the Opcode Fetch. This indicates the kind of instruction to be executed by the system. The length of this machine cycle varies between 4T to 6T states—it depends on the type of instruction. In this, the processor places the contents of the PC on the address lines, identifies the nature of machine cycle

(by IO/M , S0, S1) and activates the ALE signal. All these occur in T1 state.’’

In T2 state, RD signal is activated so that the identified memory location is read from

and places the content on the data bus (D0 – D7).

In T3, data on the data bus is put into the instruction register (IR) and also raises

the RD signal thereby disabling the memory.

In T4, the processor takes the decision, on the basis of decoding the IR, whether to enter into T5 and T6 or to enter T1 of the next machine cycle.

One byte instructions that operate on eight bit data are executed in T4. Examples are ADD B, MOV C, B, RRC, DCR C, etc.

51. Briefly describe Memory Read and Write machine cycles and show the wave- forms.

Fig. 2.14: Memory read and write machine cycle

Ans. Both the Memory Read and Memory Write machine cycles are 3T states in length. In Memory Read the contents of R/W memory (including stack also) or ROM are read while in Memory Write, it stores data into data memory (including stack memory).

As is evident from Fig. 2.14 during T2 and T3 states data from either memory or CPU are made available in Memory Read or Memory Write machine cycles respectively. The

status signal (IO/ M , S0, S1) states are complementary in nature in Memory Read and Memory Write cycles. Reading or writing operations are performed in T2.

In T3 of Memory Read, data from data bus are placed into the specified register (A,

B, C, etc.) and raises RD so that memory is disabled while in T3 of Memory Write

WR signal is raised which disables the memory.

52. Draw the I/O Read and I/O Write machine cycles and discuss.

Ans. I/O Read and Write machine cycles are almost similar to Memory Read and Write machine cycles respectively. The difference here is in the IO/ M signal status which remains 1 indicating that these machine cycles are related to I/O operations. These machine cycles take 3T states.

In I/O read, data are available in T2 and T3 states, while during the same time (T2 and T3) data from CPU are made available in I/O write.

The I/O read and write machine cycles are shown in Fig. 2.15.

Fig. 2.15: I/O read and write machine cycles

53. Draw the Interrupt Acknowledge cycles for (a) RST instruction (b) CALL instruction.

In M1, RST is decoded. This initiates a CALL to the specific vector location. Contents of the PC are stored in stack in machine cycles M2 and M3.

Fig. 2.17: Timing diagram of INTA machine cycle and execution of call instruction

The above figure shows an Interrupt Acknowledge cycle for CALL instruction. M2 and M3 machine cycles are required to call the 2 bytes of the address following the CALL. Memory write are done in machine cycles M4 and M5 in which contents of PC are stored in stack and then a new instruction cycle begins.

54. What is meant by Bus Idle Machine cycle?

Ans. There are a few situations in which machine cycles are neither Read or Written into.

These are called Bus Idle Machine cycle.

Such situations arise when the system executes a DAD or during the internal opcode generation for the RST or TRAP interrupts.

The ALE signal changes state during T1 of each machine cycle, but in Bus Idle Machine cycles, ALE does not change state.

55. Explain the DAD instruction and draw its timing diagram.

Ans. DAD instruction adds the contents of a specified register pair to the contents of H and L. For execution of DAD, 10 T-states are needed. Instead of having a single machine cycle having 10 T-states, it consists of the Opcode Fetch machine cycle (4T states) and 6

extra T-states divided into two machine cycles. These two extra machine cycles are Bus

Idle Machine cycles which do not involve either memory or I/O.

56. Discuss the concept of WAIT states in microprocessors.

Ans. So many times it may happen that there is speed incompatibility between microprocessor and its memory and I/O systems. Mostly the microprocessor is having higher speed.

So in a given situation, if the microprocessor is ready to accept data from a peripheral device while there is no valid data in the device (e.g. an ADC), then the system enters into WAIT states and the READY pin (an input pin to the microprocessor, pin no. 35 for 8085) is put to a low state by the device.

Once the device becomes ready with some valid data, it withdraws the low state on the READY pin of 8085. Then 8085 accepts the data from the peripheral by software instructions.

57. Does 8085 have multiplication and division instructions?

Ans. No, 8085 does not have the above two instructions. It can neither multiply nor divide two 8-bit numbers. The same are executed by the processor following the process of repetitive addition or subtraction respectively.

58. Indicate the bus drive capability of 8085.

Ans. 8085 buses can source up to 400 mA and sink 2 mA of current. Hence 8085 buses can drive a maximum of one TTL load.

Thus the buses need bus drivers/buffers to enhance the driving capability of the buses to ensure that the voltage levels are maintained at appropriate levels and malfunctioning is avoided.

59. What are the buffers needed with the buses of 8085?

Ans. An 8-bit unidirectional buffer 74LS244 is used to buffer the higher order address bus (A8 – A15). It consists of eight non-inverting buffers with tri-state outputs. Each pin can sink 24 mA and source 15 mA of current.

A bidirectional buffer 74LS245 (also called octal bus transreceivers) can be used to drive the bidirectional data bus (D0 – D7) after its demultiplexing. The DIR pin of the IC controls the direction of flow of data through it.

60. Explain the instruction cycle of a microprocessor.

Ans. When a processor executes a program, the instructions (1 or 2 or 3 bytes in length) are executed sequentially by the system. The time taken by the processor to complete one instruction is called the Instruction Cycle (IC).

An IC consists of Fetch Cycle (FC) and an Execute Cycle (EC). Thus IC = FC + EC. It is shown in Fig. 2.19. Depending on the type of instruction, IC time varies.

61. Explain a typical fetch cycle (FC).

Ans. The time required to fetch an opcode from a memory location is called Fetch Cycle.

A typical FC may consist of 3T states. In the first T-state, the memory address, residing in the PC, is sent to the memory. The content of the addressed memory (i.e., the opcode residing in that memory location) is read in the second T-state, while in the third T-state this opcode is sent via the data bus to the instruction register (IR). For slow memories, it may take more time in which case the processor goes into ‘wait cycles’. Most microprocessors have provision of wait cycles to cope with slow memories.

A typical FC may look like the following:

62. Draw the block schematic of a typical Instruction Word flow diagram and explain the same.

Ans. There are two kinds of words—instruction word and data word. The 2 byte content of the PC is transferred to a special register–called memory address register (MAR) or simply address register (AR) at the beginning of the fetch cycle. Since the content of MAR is an address, it is thus sent to memory via the address bus. The content of the addressed memory is then read under ‘Read control’ generated by T&C section of the microprocessor. This is then sent via the data bus to the memory data register (MDR) or simply data register (DR) existing in CPU. This is placed in the instruction register (IR) and is decoded by the instruction decoder and subsequently executed. The PC is then incremented if the subsequent memory location is to be accessed.

63. Draw the block schematic of a typical data word flow diagram and explain the same.

Ans. The data word flows via the data bus into the accumulator. The data source can be a memory device or an input device. Data from the accumulator is then manipulated in ALU under control of T & C unit. The manipulated data is then put back in the accumulator and can be sent to memory or output devices.

The block schematic of data flow is shown below.

64. Why a microprocessor based system is called a sequential machine?

Ans. It can perform the jobs in a sequential manner, one after the other. That is why it is called a sequential machine.

65. Why a microprocessor based system is called a synchronous one?

Ans. All activities pertaining to the µP takes place in synchronism with the clock. Hence it is called a synchronous device.

66. Draw the diagram which will show the three buses separately, with the help of peripheral ICs.

Ans. The scheme of connections is shown below. The octal bus driver 74LS244 drives the higher order address bus A15 – A8 while 74LS373 Latch drives the lower order address bus A7 – A0 (with the help of ALE signal). The bidirectional bus driver 74LS245 drives the

data bus D7 – D0 while the 74LS138 (a 3 to 8 decoder chip) outputs at its output pins IOW, IOR, MEMW, MEMR, signals from the IO/ M , RD and WR signals of 8085.

Fig. 2.23: Demultiplexing of address/data bus and separation of control signals

67. Discuss the status of WR and RD signals of 8085 at any given instant of time.

Ans. At any given instant, the status of the two signals WR and RD will be complementary

to each other.

It is known that microprocessor based system is a sequential device, so that at any given point of time, it does the job of reading or writing—and definitely not the two jobs

at the same time. Hence if WR signal is low, then RD signal must be high or vice versa.

68. Which registers of 8085 are programmable?

Ans. The registers B, C, D, E, H and L are programmable registers in that their contents can be changed by programming.

69. Suggest the type of operations possible on data from a look of the architecture of 8085.

Ans. The architecture of 8085 suggests that the following operations are possible.

z Can store 8-bits of data.

z Uses the temporary registers during arithmetic operations.

z Checks for the condition of resultant data (like carry, etc.) from the flag register.

70. What are the externally initiated operations supported by 8085?

Ans. 8085 supports several externally initiated operations at some of its pins. The operations possible are:

z Resetting (via Reset pin)

z Interruptions (via Trap, RST 7.5, RST 6.5, RST 5.5 and Interrupt pin)

z Ready (via Ready pin)

z Hold (via Hold pin)

71. Name the registers not accessible to the programmer. Ans. The following registers cannot be accessed by the programmer:

z Instruction register (IR)

z Memory address register (MAR) or supply address register (AR)

z Temporary registers.

72. Name the special purpose registers of 8085.

Ans. The special purpose registers used in 8085 microprocessor are:

z Accumulator register (A)

z Program counter register (PC)

z Status (or Flag) register

z Stack pointer register (SP)

73. What should be the size of the Instruction Register if an arbitrary microprocessor has only 25 instructions?

Ans. The length of the Instruction Register would be 5-bits, since 25 = 32, since a 5-bit Instruction Register can decode a maximum of 32 instructions.

74. Explain the difference between HLT and HOLD states.

Ans. HLT is a software instruction. Its execution stops the processor which enters into a HALT state and the buses of the processor are driven into tri-state.

HOLD is an hardware input to the processor. When HOLD input = 1, the processor goes into the HOLD state, but the buses don’t go into tri-state. The processor gives out a high HLDA (hold acknowledge) signal which can be utilised by an external device (like a DMA controller) to take control of the processor buses. HOLD is acknowledged by the processor at the end of the current instruction execution.

75. Indicate the length of the Program Counter (PC) to access 1 KB and 1 MB memory.

Ans. 1 KB = 1024 bytes

and 1 MB = 1024 K bytes

Thus the required number of bits in PC to access 1 KB are 10 (210 = 1024) and 20 (220 = 1024 K) respectively.

76. What determines the number of bytes to be fetched from memory to execute an instruction?

Ans. An instruction normally consists of two fields. These are:

Thus, while the system starts executing an instruction, it first decodes the opcode which then decides how many more bytes are to be brought from the memory—its minimum value is zero (like RAR) while the maximum value is two (like STA 4059 H).

77. A Microprocessor’s control logic is ‘microprogrammed’. Explain.

Ans. It implies that the architecture of the control logic is much alike the architecture of a

very special purpose microprocessor.

78. Does the ALU have any storage facility?

Ans. No, it does not have any storage facility. For this reason, the need for temporary data

registers arise in ALU–it has two inputs: one provided by the accumulator and the other

from the temporary data register. The result of summation is stored in the accumulator.

Microprocessor, Microcomputer and Associated Languages

Posted on October 21, 2014 by Farahat Leave a comment

Microprocessor, Microcomputer and Associated Languages

1. On which model is based the basic architecture of a digital computer? Ans. The basic architecture of a digital computer is based on Von Neumann model.

2. What is meant by distributed processing?

Ans. Distributed processing involves the use of several microprocessors in a single computer system. For example, for such a system, the first microprocessor may control keyboard activities, the second controls storage devices like disk drives, the third controls input/ output operations, while the fourth may act as the main system processor.

3. When was the first microprocessor developed?

Ans. The first microprocessor was developed by BUSICOM of Japan and INTEL of USA in the year 1971.

4. What is a microprocessor?

Ans. A microprocessor may be thought of as a silicon chip around which a microcomputer is built.

5. What is the technology used in microprocessors? Ans. NMOS technology is used in microprocessors.

6. What are the three main units of a digital computer?

Ans. The three main units of a digital computer are: the central processing unit (CPU), the memory unit and the input/output devices.

7. How does the microprocessor communicate with the memory and input/output devices?

Ans. The microprocessor communicates with the memory and the Input/Output devices via the three buses, viz., data bus, address bus and control bus.

8. What are the different jobs that the CPU is expected to do at any given point of time?

Ans. The CPU may perform a memory read or write operation, an I/O read or write operation or an internal activity.

9. What is a mnemonic?

Ans. It is very difficult to understand a program if it is written in either binary or hex code.

Thus the manufacturers have devised a symbolic code for each instruction, called a

mnemonic.

Examples of mnemonics are: INR A, ADD M, etc.

10. What is machine language programming?

Ans. Programming a computer by utilising hex or binary code is known as machine language programming.

11. What is meant by assembly language programming?

Ans. Programming a microcomputer by writing mnemonics is known as assembly language programming.

12. What are meant by low level and high level languages?

Ans. Programming languages that are machine dependent are called low level languages. For example, assembly language is a low level language.

On the other hand, programming languages that are machine independent are called high level languages. Examples are BASIC, FORTRAN, C, ALGOL, COBOL, etc.

13. What is meant by ‘word length’ of a computer?

Ans. The number of bits that a computer recognises and can process at a time is known as its ‘word length’.

14. What is meant by instruction?

Ans. An instruction is a command which asks the microprocessor to perform a specific task or job.

15. How many different instructions mP 8085 has? What is an instruction set?

Ans. 8085 microprocessor has a total of 74 different instructions for performing different operations or tasks.

The entire different instructions that a particular microprocessor can handle is called its instruction set.

16. What an instruction consists of?

Ans. An instruction consists of an operation code (called ‘opcode’) and the address of the data (called ‘operand’), on which the opcode operates.

17. Give one example each of the different types of instructions.

Ans. Instructions can be of (i) direct (ii) immediate (iii) implicit type. Examples of each type follows:

(i) direct type : LDA 4000

(ii) immediate type : MVIA, 1F

(iii) implicit type : ADD C

18. What language a microprocessor understands? Ans. Microprocessor understands only binary language.

19. How the mnemonics written in assembly language are translated into binary?

Ans. The translation from assembly language (i.e., mnemonics) into binary is done either manually (known as hand (or manual) assembly) or by a program called an assembler.

Thus an assembler can be thought of as a program which translates the mnemonics entered by an ASCII keyboard into its equivalent binary code, which is the only one understood by a microprocessor.

20. How an assembler translates programs written in mnemonic form to binary?

Ans. An assembler has a ‘translation dictionary’, which is stored in its memory. Mnemonics entered via keyboard is compared with this dictionary, which then retrieves its binary equivalent from the same place (dictionary).

21. What are the types of mnemonics possible?

Ans. Mnemonics can be of two types—alphabetical or alphanumerical.

Example of first type is ADD D whereas, MVI A, 0F is an example of the second category.

22. What are source codes and object codes?

Ans. High level languages (like, BASIC, COBOL, ALGOL, etc.) are called source codes, whereas binary language is called object code.

23. How are high level languages converted into binary?

Ans. The high level languages are converted into their corresponding binary by means of another program, called either a compiler or an interpreter.

Compilers are generally used for FORTAN, PASCAL, COBOL, etc. whereas

interpreters are generally used in BASIC. M-BASIC is a common example of an

interpreter for BASIC language.

24. What is a ‘statement’?

Ans. Instructions written in high level languages are known as statements.

25. Write down the difference between a compiler and an interpreter.

Ans. Difference between a compiler and an interpreter lies in the generation of the machine code or object code.

A compiler reads the entire program first and then generates the corresponding object code.

Whereas, an interpreter reads an instruction at a time, produces the corresponding object code and executes the same before it starts reading the next instruction. A program from a compiler runs some 5 to 25 times faster than a program from an interpreter.

26. Differentiate between a compiler/interpreter and an assembler. Ans.

S.No.	Compiler/Interpreter	Assembler
1.	Debugging easier	Debugging relatively tougher
2.	Less efficient	More efficient
3.	Requires large memory space	Requires less memory space

As an example, for gadget controls and traffic signals, assembly language programming is done because programs in such cases are compact and not lengthy. But for cases where large program lengths are a must, compilers/interpreters are used. For such a case, although a large memory space is required, the advantage lies in very quick debugging.

27. What are the names given to instructions written in high and low level languages?

Ans. The instructions written in high level languages are known as ‘statements’ whereas those written in low level languages are called ‘mnemonics’.

28. What is another name of a microprocessor?

Ans. A microprocessor is also called the CPU, the central processing unit.

29. What is a microcomputer?

Ans. A microcomputer is a system which is capable of processing a stream of input informations and will generate a stream of output informations taking the help of a program which is stored in the memory of the system.

30. What are the jobs that a microcomputer is capable of doing? How does it do the jobs?

Ans. A microcomputer is capable of doing the following jobs:

(a) receiving input (in the form of data or instruction).

(b) performing computations, both arithmetic and logical.

(d) displaying the results of any computations.

(e) controlling all the devices that perform the above mentioned four tasks, either

directly or indirectly.

The first task is done by an input device, whereas the second job is done by the arithmetic logic unit (ALU). The third task is done by the memory unit while an output device does the fourth job.

The fifth job is executed by the timing and control (T&C) unit.

31. What is a bus?

Ans. A bus is a bunch of wires through which data or address or control signals flow.

32. What are the different buses and what jobs they do in a microprocessor?

Ans. The different buses in a microprocessor are the data bus (DB), address bus (AB) and the control bus (CB). Data flow through the DB, while address comes out of the AB and CB controls the activities of the microcomputer system at any instant of time.

33. Why are the different buses buffered?

Ans. A buffer enhances the current or power driving capability of a pin of an IC.

34. In how many ways computers are divided?

Ans. Computers are divided into three categories as per the superiority and number of microprocessors used. These are:

z Micro computers

z Mini computers

z Mainframe computers

35. Distinguish between the three types of computers.

Ans. A microcomputer is a small computer containing only a single central processing unit (CPU). Their word length varies between 8 and 32 bits and used in small industrial and process control systems. The storage capacity and speed requirements of micro computers are moderate.

Mini computers are having more storage capacity and more speed than micro computers. Mini computers are used in research, data processing, scientific calculations etc.

Mainframe computers are designed to work at very high speed and they have very high storage capacity. Their word length is typically 64-bits. These are used for research, data processing, graphic applications, etc.

36. In how many ways computer softwares are categorised?

Ans. Computer softwares are divided into two broad categories—system software and user software.

37. Explain the two types of softwares.

Ans. System software is a collection of programs used for creation, preparation and execution of other programs. Editors, assemblers, loaders, linkers, compilers, interpreters, debuggers and OS (operating system) are included in system software.

User software are softwares developed by various users.

38.Draw the software hierarchy of a microcomputer system. Ans. The software hierarchy is shown below:

Fig. 1.1: Software hierarchy of a microcomputer system

39. What is an editor?

Ans. An editor is a program and is used for creation and modification of source programs or text. The editor program includes commands which can delete, insert or change lines/ characters.

An editor stores in ASCII form in successive RAM locations of the typed letters/ numbers. This then can be saved by the SAVE command on a floppy or hard disk. The editor can load the program on RAM later for corrections/alterations, if necessary.

40. What is an OS (operating system) and what are its functions?

Ans. An operating system provides an interface between the end user and the machine. It performs the function of resource management. By ‘resource’ is meant a microprocessor, memory or an I/O device.

An OS is a collection of a set of programs that manages machine functions under varied conditions.

The different functions performed by the OS include an efficient or effective way of sharing memory, I/Os and the CPU amongst different users. Today, operating systems are DOS, UNIX, WINDOWS, etc.

41. What are the different types of assemblers used?

Ans. The different assemblers used are: (a) Macro Assembler, (b) Cross Assembler, (c) Meta Assembler.

42. What is a linker?

Ans. A linker is a program that links several small object files to produce one large object file.

A large program is usually divided into several small programs. They are written separately, tested and debugged. The large program is then produced by linking these debugged programmes.

A linker has a link file and a link map. The former contains the binary codes of all the modules which have been combined while the link map stores in it the addresses of all the link files. A linker assigns relative addressing instead of absolute addressing which helps in putting a linker program anywhere in the memory.

43. What is a locator?

Ans. A locator is a program which is used to assign specific address when object code is to be loaded into the memory.

44. What are the different assembly languages used for 8085 microprocessor?

Ans. Two different assembly languages are used for 8085 microprocessor—one is used by the manufacturer INTEL and the other defined in IUL 77.

45. What is a coprocessor?

Ans. A coprocessor or an arithmetic coprocessor, as it is so called, performs operations like exponentiation, trigonometric functions, etc. To implement these functions in CPU hardware is a costly one and the software implementation of the above slows down the processor. A coprocessor overcomes these difficulties.

The coprocessor has its own instruction set. The CPU and the coprocessor execute their respective instructions from the same program.

The instructions belonging to the coprocessor are fetched and decoded by the CPU but executed by the coprocessor.

46. Draw a typical coprocessor configuration and discuss the same. Ans. A typical coprocessor configuration looks like as follows:

The CPU and the coprocessor share the same clock, bus control logic and also share the entire memory and the I/O subsystem. In normal configuration, CPU is the master and the coprocessor is the slave.

The CPU treats the coprocessor as an external memory in the sense that the CPU can read from/write into the coprocessor registers in a manner alike that of an external memory. The CPU and the coprocessor executes their instructions independent of each other. When the coprocessor executes instructions, it indicates the CPU about its

executions via the ‘BUSY’ signal.

47. What is a coprocessor trap?

Ans. When a coprocessor is not connected in the system and the functions of the coprocessor is done by the CPU by writing coprocessor instructions from a predetermined location in the form of a software routine and invoked by interrupt, it is known as ‘coprocessor trap’.

48. Explain the three fields contained in a coprocessor instruction.

Ans. There are three fields in a coprocessor instruction—these are code, address and opcode.

The code field distinguishes between the coprocessor and CPU instructions. The address field indicates the address of a particular coprocessor. This is required when several coprocessors are used in the system. The opcode field indicates the type of operation to be executed by the processor.

49. What is a debugger?

Ans. A debugger is a program that debugs an object code program by placing it into the system memory and subsequently executing the same.

50. How does a debugger help in debugging a program?

Ans. A debugger is a software tool which isolates the problems/drawbacks in a programmer’s program.

A debugger helps in debugging a program in the following ways:

(a) A debugger helps in checking the contents of memory locations and various registers and

also alter the same if required and rerun the program to check the correctness of the

modified program.

(b) Program execution can be stopped after each instruction–hence step by step checking is

possible with a debugger.

A program then can run up to the breakpoint address and not beyond. Thus any fault

in the program up to the breakpoint address can be checked by having a look at the

various registers and memory contents. If no fault occurs the breakpoint is set at a latter

address in the program and the debugger can again be rerun to check for the correctness

of the program. This way the whole program can be corrected by judiciously inserting

breakpoints in a program.

51. What is meant by the term ‘word’?

Ans. A collection of bits is called a word. A word does not have a fixed number of bits—unlike

the case of byte (= 8 byte) or a nibble (= 4 bytes).

For different microprocessors, the word length varies. For example, for 8-bit

microprocessors, the word length is 8-bits while that for 32-bit microprocessors, the word

length is 32-bits.

A word is expressed usually in multiples of 2, but no value is excluded. That is, we

can have a 19-bit word or 37-bit word, etc.

52. What is meant by the term ‘long word’?

Ans. The term ‘long word’ means a group of bits twice the normal length of the

microprocessor. Hence, for a 16-bits microprocessor like 8086, a long word means

a group consisting of 32-bits.

53. Distinguish between KB, MB, GB, TB and PB.

Ans. These stand for Kilobyte, Megabyte, Gigabyte, Terabyte and Petabyte respectively.

1 KB	=	1024 bytes	=	210 bytes
1 MB	=	1 Kilo KB	=	220 bytes
1 GB	=	1 Kilo MB	=	230 bytes
1 TB	=	1 Kilo GB	=	240 bytes
1 PB	=	1 Kilo TB	=	250 bytes

54. Compare signed magnitude number and complementary numbers. Ans. The comparison is made on the basis of an 8-bit word.

In signed magnitude number system, MSB represents the sign of the number with 1 and 0 representing minus and plus, respectively. This number system has the following drawbacks:

Using the MSB for sign bit leaves 7-bits for data which can range from 0 to 12710 ( = 11111112) while 8-bits can manage numbers from 0 to 25510 (=1111 11112).

Addition of two signed numbers does not give the correct result always. An example follows:

Thus the result of addition of the two numbers is –0710, but it should have been

+13510.

Use of complementary numbers (usually 2’s complement of a binary number is used)

gives rise to the following advantages:

z For an 8-bit data, the data values can vary from 0 to 25510 (= 1111 11112)

z Addition and subtraction can be implemented with almost same circuitry.

55. What is meant by normalising a number?

Ans. When a number 4751 is converted to 4.751×103, the latter is called the normalised version

of the former.

Likewise, in binary, a number 1011 1101 can be normalised to 1.0111101 × 28.

Another binary number 0.0001101 is normalised to 1.101 × 2–4.

If a given binary number is in a form 1.0101101, then it is already in the normalised

form.

56. Name the different parts of a normalised number. Ans. Let a binary number is 1.01101 × 1011. Then

Hence, a normalised binary number consists of mantissa, radix and exponent.

57. Discuss the utility of floating point numbers.

Ans. Floating point numbers are useful when the system has either to handle extremely large

numbers (as in Astronomy) or very small ones (as in Nuclear Physics). For floating point

numbers, the binary number starts with a 1, followed by the binary point. An 8-bit binary

mantissa can assume extreme values as 1.0000000 to 1.1111111.

While storing such floating point numbers, the mandatory 1 followed by the binary

point can safely be ignored—thereby saving previous storage space. It is assumed that

the 1 and the binary point are just present. Thus the above can now be stored as 0000000

to 1111111.

For floating point numbers, a 32-bit storage area is used. Many variants are there

to fill in these 32-bits, but the following figure is the one that is most sought after.

Fig. 1.3: Floating point numbers—32-bit storage area

Bit 0 is the sign bit for the mantissa. Bits 1 to 23 hold the mantissa while bits 24 to 31 hold the exponent of the number. The eight bits (bits 24 to 31) are used to hold the numbers from –127 to +128 in 2’s complement form or Excess –127 form. In Excess –127 notation, 127 is added to the original exponent value (in decimal)—this is done to get rid of the negative exponent values. Thus this modified exponent value (positive) is stored in bits 24 to 31 after it is converted into binary.

58. Discuss speed, size and accuracy while handling floating point numbers.

Ans. Floating point operations that can be carried out per second is a measure of the speed—

abbreviated as FLOPS.

Accuracy is dependent on the number of mantissa bits. More number of mantissa

bits result in more accuracy. Bits 1 to 23, meant for mantissa, can have a maximum

binary value of 1.1111 1111 1111 1111 1111 111. The 1’s, starting from the binary point

on the right, have their decimal values +0.5, +0.25, +0.125, +0.0625, etc. Thus, when

the 24-bits are converted into decimal, it will approach a value of 2 — but will never

equal it. If more number of bits are accommodated in mantissa (i.e., mantissa will now

have more than the normal 24-bits), then the converted decimal equivalent will be

having a value which will be even more closer to 2. Thus increasing number of mantissa

bits result in more accuracy.

Size is dependent on the number of exponent bits. More number of exponent bits

results in greater size of the number that can be handled. Bits 24 to 31, meant for

exponent, has eight bits ranging from –127 to +128. Thus the maximum number that can be handled is 1 × 2128 = 3.4 × 1038 roughly. This value would have been more if in case more number of bits are accommodated into exponent bits. Thus increasing number of exponent bits results in greater size of the number that can be handled. In conclusion, when more accuracy is demanded, number of mantissa bits are to be increased (instead of the normal 24-bits) and in cases of higher size of data handling, number of exponent bits are to be increased (instead of the normal 8-bits) within the 32-bit storage space.

59. Explain single and double precision.

Ans. Single and double precision mean 32-bits and 64-bits storage areas respectively. The

extra storage space made available from single to double precision—utilised for

accommodating more number of mantissa bits—would result in much more accuracy from the system.

60. List the different generation languages.

Ans. These are first, second, third and fourth generation languages. Machine code belongs to

first generation, while Assembly Language belongs to second generation language. First

and second generation languages are known as low level languages. Third generation languages include FORTRAN, BASIC, COBOL, PASCAL, C, C++, JAVA while fourth generation languages are LISP, APL, PROLOG, etc.

Fig. 1.4: The different languages

AC motor What It Does,How It Works,Variants,Values,How to Use it and What Can Go Wrong

Posted on October 20, 2014 by Farahat Leave a comment

The distinction between AC and DC motors has become blurred as controllers for DC motors make increasing use of pulse-width modulation, which can be viewed as a form of alternating current. All motors that consume DC power are referenced in the DC motor section of this encyclopedia, regardless of whether they modulate the power internally. Stepper motors and servo motors are considered as special cases, each with its own entry. AC motors, described here, are those that consume alternating current, usu ally in the form of a sine wave with a fixed frequency.

What It Does

An AC motor uses a power supply of alternating current to generate a fluctuating magnetic field that turns a shaft.

How It Works

The motor consists primarily of two parts: the stator, which remains stationary, and the rotor, which rotates inside the stator. Alternating cur rent energizes one or more coils in the stator, creating fluctuating magnetic fields that interact with the rotor. A simplified representation is shown in Figure 23-1, where the coils create mag netic forces indicated by the green arrows, N rep resenting North and S representing South.

Stator Design

Plug-in electric fans typically use AC motors. The stator from a large electric fan is shown in Figure 23-2, where the large diameter of each coil

Figure 23-1. A simplified representation of a basic AC motor. The green arrows indicate magnetic force.

maximizes its magnetic effect. The stator from a smaller electric fan is shown in Figure 23-3, in which only one coil is used. (The coil is wrapped in black electrical tape.)

Figure 23-2. The stator from a large electric fan. Each coil of copper wire is centered on a lug pointing inward to the hole at the center, where the rotor would normally be mounted. The coils overlap because their diameter is maximized to increase their magnetic effect. Each coil is tapped to allow speed selection in steps via an external rotary switch.

The core of a stator resembles the core of a transformer in that it usually consists of a stack of wafers of high-silicon steel (or sometimes aluminum or cast iron). The layers are insulated from one another by thin layers of shellac (or a similar compound) to prevent eddy currents that would otherwise circulate through the entire thickness of the stator, reducing its efficiency.

The coil(s) wound around the stator are often re ferred to as field windings, as they create the magnetic field that runs the motor.

Rotor Design

In most AC motors, the rotor does not contain any coils and does not make any electrical con

Figure 23-3. This stator from a smaller electric fan uses only a single coil, wrapped in black tape. It is sufficient to induce a magnetic field but is generally less efficient than a motor using multiple coils.

nection with the rest of the motor. It is powered entirely by induced magnetic effects, causing this type of motor to be known generally as an induction motor.

As the AC voltage changes from positive to negative, the magnetic force induced in the stator collapses and a new field of opposite polarity is created. Because the stator is designed to create an asymmetrical field, it induces a rotating magnetic field in the rotor. The concept of a rotating magnetic field is fundamental in AC motors.

Like the stator, the rotor is fabricated from wafers of high silicon steel; embedded in the wafers are nonmagnetic rods, usually fabricated from aluminum but sometimes from copper, oriented approximately parallel to the axis of rotation. The rods are shorted together by a ring at each end of the rotor, forming a conductive “cage,” which explains why this device is often referred to colloquially as a squirrel cage motor.

Figure 23-4 shows the configuration of a rotor cage with the surrounding steel wafers removed for clarity. In reality, the rods in the cage are al most always angled slightly, as shown in Figure 23-5, to promote smooth running and re duce cogging, or fluctuations in torque, which would otherwise occur.

Figure 23-4. The rotor of a typical AC motor contains a cage of aluminum (or sometimes copper) in which eddy currents occur, as a result of the rotating magnetic field inside the steel body of the rotor (which is omitted here for clarity). These currents cause their own magnetic fields, which interact with the fields generated by coils in the stator.

In Figure 23-6, the steel wafers of a rotor are shown, with channels to accommodate an angled aluminum cage. Figure 23-7 shows a cross- section of a rotor with the cage elements in pale red and the steel wafer in gray.

Figure 23-5. To promote smooth running of the motor, the longitudinal elements of the cage are typically angled, as suggested in this rendering.

Figure 23-6. The steel wafers in the rotor of an AC motor are typically offset as shown here. The channels are to ac- commodate a cage of aluminum or copper conductors.

Figure 23-7. Cross-section of a rotor with steel shown in gray and embedded elements of an aluminum cage shown in pale red.

The actual rotor from an induction motor is shown in Figure 23-8. This rotor was removed from the stator shown in Figure 23-3. The bear ings at either end of the rotor were bolted to the stator until disassembly.

Although the cage is nonmagnetic, it is electrically conductive. Therefore the rotating magnetic field that is induced in the steel part of the rotor generates substantial secondary electric current in the cage, so long as the magnetic field inside the rotor is turning faster than the rotor itself. The current in the longitudinal elements of the cage creates its own magnetic field, which interacts with the fields created by coils in the stator. At traction and repulsion between these fields causes the rotor to turn.

Note that if the turning speed of the rotor rises to match the frequency of the alternating current powering the coils in the stator, the cage in the rotor is no longer turning through magnetic lines of force, and ceases to derive any power from

Figure 23-8. The rotor from a small fan motor. The aluminum cage and its end pieces are the pale gray sections, steel plates are the darker sections.

them. In an ideal, frictionless motor, its unloaded operating speed would be in equilibrium with the AC frequency. In reality, an induction motor never quite attains that speed.

When power is applied while the rotor is at rest, the induction motor draws a heavy surge of cur rent, much like a short-circuited transformer. Electrically, the coils in the stator are comparable to the primary winding of a transformer, while the cage in the rotor resembles the secondary winding. The turning force induced in the stationary rotor is known as locked-rotor torque. As the motor picks up speed, its power consumption diminishes. See Figure 23-9.

When the motor is running and a mechanical load is applied to it, the motor speed will drop. As the speed diminishes, the cage of conductors embedded in the rotor will derive more power, as they are turning more slowly than the rotating magnetic field. The speed of rotation of the field is determined by the frequency of the AC power, and is therefore constant. The difference in rota

Figure 23-9. An approximated graph showing the typical current consumption of an AC induction motor as it starts from rest and gains speed over a period of time.

tional speed between the magnetic field and the rotor is known as slip. Higher levels of slip induce greater power, and therefore the induction motor will automatically find an equilibrium for any load within its designed range.

When running under full load, a small induction motor may have a slip value from 4 to 6 percent. In larger motors, this value will be lower.

Variants

Variants of the generic induction motor de scribed above are generally designed to take ad vantage of either single-phase or three-phase al ternating current.

A synchronous motor is a variant in which the ro tor maintains a constant speed of rotation regardless of small fluctuations in load.

Some AC motors incorporate a commutator, which allows an external connection to coils mounted on the rotor, and can enable variable speed control.

A linear motor may consist of two rows of coils, energized by a sequence of pulses that can move a permanent magnet or electromagnet between the coils. Alternatively, the linear motor’s coils may move as a result of magnetic interaction with a segmented fixed rail. Detailed description of linear motors is outside the scope of this en cyclopedia.

Single-Phase Induction Motor

The majority of induction motors run on single- phase alternating current (typically, from domes tic wall outlets). This type of motor is not innately self-starting because the stator coils and rotor are symmetrical. This tends to result in vibration rather than rotation.

To initiate rotation, the stator design is modified so that it induces an asymmetrical magnetic field, which is more powerful in one direction than the other. The simplest way to achieve this is by adding one or more shorting coils to the stator. Each shorting coil is often just a circle of heavy- gauge copper wire. This ploy reduces the efficiency of the motor and impairs its starting tor que, and is generally used in small devices such as electric fans, where low-end torque is unimportant. Because the shorting coil obstructs some of the magnetic field, this configuration is often known as a shaded pole motor.

Copper shorting coils are visible in the fan motor shown in Figure 23-3.

A capacitor is a higher-cost but more efficient alternative to a shorting coil. If power is supplied to one or more of the stator coils through a capacitor, it will create a phase difference between these coils and the others in the motor, inducing an asymmetrical magnetic field. When the motor reaches approximately 80% of its designed running speed, a centrifugal switch may be included to take the capacitor out of the circuit, since it is no longer necessary. Switching out the capacitor and substituting a direct connection to the stator coils will improve the efficiency of the motor.

A third option to initiate rotation is to add a second winding in the stator, using fewer turns of smaller-gauge wire, which have a higher resist ance than the main winding. Consequently the magnetic field will be angled to encourage the motor to start turning. This configuration is known as a split-phase induction motor, in which the starter winding is often referred to as the auxilliary winding and consists of about 30% of the total stator windings in the motor. Here again, a centrifugal switch can be incorporated, to eliminate the secondary winding from the circuit when the motor has reached 75 to 80 per cent of its designed running speed.

The relationship between motor speed and torque of the three types of motors described above is shown in Figure 23-10. These curves are simplified and do not show the effect that would be produced by introducing a centrifugal switch.

Figure 23-10. Approximate curves showing the relation- ship between speed and torque for three types of single- phase induction motor. (Graph derived from AC Induction Motor Fundamentals published by Microchip Technology Inc.)

Three-Phase Induction Motor

Larger induction motors are often three-phase

devices. Three-phase AC (which is by far the most

common form of polyphase AC) is delivered by a power utility company or generator via three wires, each of which carries alternating current with a phase difference of 120 degrees relative to the other two, usually for industrial applica tions. A common configuration of stator coils for a three-phase motor is shown in Figure 23-11. Since the three wires take it in turns to deliver their peak voltage, they are ideally suited to turn the stator of a motor via induction, and no shorting coil or capacitor is needed for startup. Heavy- duty 3-phase induction motors are extremely re liable, being brushless and generally maintenance-free.

Synchronous Motor

A synchronous motor is a form of induction mo tor that is designed to reach and maintain equilibrium when the rotor is turning in perfect syn chronization with the AC power supply. The speed of the motor will depend on the number of poles (magnetic coils) in the stator, and the number of phases in the power supply. If R is the RPM of a synchronous motor, f is the frequency of the AC current in Hz, and p is the number of poles per phase:

R = (120 * f) / p

This formula assumes 60Hz AC current. In nations where 50Hz AC is used, the number 120 should be replaced with the number 100.

Two basic types of synchronous motors exist: di rect current excited, which require external power to start turning, and non-excited, which are self- starting. Since non-excited synchronous motors are more common in electronic applications, this encyclopedia will not deal with direct current ex cited variants.

A hysteresis motor is a synchronous motor con taining a solid rotor cast from cobalt steel, which has high coercivity, meaning that once it is mag netized, a substantial field is required to reverse the magnetic polarity. Consequently the polarity of the rotor lags behind the constantly changing

Figure 23-11. The graph shows voltage delivered via three wires constituting a three-phase power supply. (The curve colors are arbitrary.) A three-phase motor contains a multiple of three coils—often six, as shown here diagrammatically. The three wires of the power supply are connected directly to the coils, which induce a rotating magnetic field.

polarity of the stator, creating an attracting force that turns the rotor. Because the lag angle is in dependent of motor speed, this motor delivers constant torque from startup.

Reluctance Motor

Reluctance is the magnetic equivalent to electrical resistance. If a piece of iron is free to move in a magnetic field, it will tend to align itself with the field to reduce the reluctance of the magnetic

circuit. This principle was used in very early reluctance motors designed to work from AC and has been revived as electronics to control variable frequency drives have become cheaper.

The simplest reluctance motor consists of a soft iron rotor with projecting lugs, rotating within a stator that is magnetically energized with its own set of inwardly projecting poles. The rotor tends to turn until its lugs are aligned with the poles of the stator, thus minimizing the reluctance.

A basic reluctance motor design is shown in Figure 25-2. It is located in the stepper motor section of this encyclopedia, as stepper motors are a primary application of the reluctance principle.

Although a reluctance motor can be used with polyphase fixed-frequency AC power, a variable frequency drive greatly enhances its usefulness. The timing of the frequency is adjusted by the speed of the motor, which is detected by a sensor. Thus the energizing pulses can remain “one step ahead” of the rotor. Since the rotor is not a mag net, it generates no back-EMF, allowing it to reach very high speeds.

The simplicity of the motor itself is a compensating factor for the cost of the electronics, as it re quires no commutator, brushes, permanent magnets, or rotor windings. Characteristics of re luctance motors include:

• Cheap parts, easily manufactured, and high reliability.

• Compact size and low weight.

• Efficiencies greater than 90% possible.

• Capable of high start-up torque and high speed operation.

Disadvantages include noise, cogging, and tight manufacturing tolerances, as the air gap be tween the rotor and stator must be minimized.

A reluctance motor can function synchronously, if it is designed for that purpose.

Variable Frequency Drive

A basic induction motor suffers from significant problems. The surge of power that it draws when starting from rest can pull down the supply volt age enough to affect other devices that share the AC power supply. (Hence, the brief dimming of lights that may occur when the compressor in an air conditioner or refrigerator starts running.) While the motor is turning, it can introduce electrical noise, which feeds back into the power supply, once again causing potential problems for other devices. In addition, the narrow range of speed of an AC induction motor is a great dis advantage.

The advent of cheap solid-state technology encouraged the development of variable-frequency power supplies for induction motors. Because the impedance of the motor will diminish as the frequency diminishes, the current drawn by the motor will tend to increase. To prevent this, a variable frequency supply also varies the voltage that it delivers.

Wound-Rotor AC Induction Motor

The stator of this variant is basically the same as that of a single-phase induction motor, but the rotor contains its own set of coils. These are electrically accessible via a commutator and brushes,

as in a DC motor. Because the maximum torque

(also known as pull-out torque) will be prop or tional to the electrical resistance of the coils in the rotor, the characteristics of the motor can be adjusted by adding or removing resistance externally, via the commutator. A higher resistance will enable greater torque at low speed when the slip between the rotor speed and rotation of the magnetic field induced by the stator is greatest. This is especially useful in corded power tools such as electric drills, where high torque at low speed is desirable, yet the motor can accelerate to full speed quickly when the external resistance is reduced. Typically, the resistance is adjusted via the trigger of the drill.

Figure 23-12 shows a wound-rotor AC induction motor. The disadvantage of this configuration is

the brushes that supply power to the rotor will eventually require maintenance. Much larger wound-rotor motors are also used in industrial applications such as printing presses and eleva tors, where the need for variable speed makes a simple three-phase motor unsuitable.

Figure 23-12. A motor in a corded electric drill uses coils in a brushed rotor to enable variable speed output. In most AC motors, the speed is not adjustable and the rotor does not make any electrical connection with the rest of the motor.

Universal Motor

A wound-rotor motor may also be described as a universal motor if its rotor and stator coils are connected in series. This configuration allows it to be powered by either AC or DC.

DC supplied to the rotor and the stator will cause mutual magnetic repulsion. When the rotor

turns, the brushes touching the split commutator reverse the polarity of voltage in the rotor coils, and the process repeats. This configuration is very similar to that of a conventional DC motor, except that the stator in a universal motor uses electromagnets instead of the permanent mag nets that are characteristic of a DC motor.

When powered by AC, the series connection be tween stator and rotor coils insures that each pulse to the stator will be duplicated in the rotor, causing mutual repulsion. The addition of a shorting coil in the stator provides the necessary asymmetry in the magnetic field to make the motor start turning.

Universal motors are not limited by AC frequency, and are capable of extremely high-speed operation. They have high starting torque, are com pact, and are cheap to manufacture. Applications include food blenders, vacuum cleaners, and hair dryers. In a workshop, they are found in routers and miniature power tools such as the Dremel series.

Because a universal motor requires commutator and brushes, it is only suitable for intermittent use.

Inverted AC Motors

Some modern domestic appliances may seem to contain an AC motor, but in fact the AC current is rectified to DC and is then processed with pulse-width modulation to allow variable speed control. The motor is really a DC motor; see the entry on this type of motor for additional information.

Values

Because a basic AC induction motor is governed by the frequency of the power supply, the speed of a typical four-pole motor is limited to less than 1,800 RPM (1,500 RPM in nations where 50Hz AC is the norm).

Variable-frequency, universal, and wound-rotor motors overcome this limitation, and can reach

speeds of 10,000 to 30,000 RPM. Synchronous motors typically run at 1,800 or 1,200 RPM, de pending on the number of poles in the motor. (They run at 1,500 or 1,000 RPM in locations where the frequency of AC is 50Hz rather than 60Hz).

For a discussion of the torque that can be created by a motor, see “Values” (page 184) in the DC motor entry in this encyclopedia.

How to Use It

Old-fashioned record players (where a turntable supports a vinyl disc that must rotate at a fixed speed) and electric clocks (of the analogue type) were major applications for synchronous motors, which used the frequency of the AC power sup ply to control motor speed. These applications have been superceded by CD players (usually powered by brushless DC motors) and digital clocks (which use crystal oscillators).

Many home appliances continue to use AC- powered induction motors. Small cooling fans for use in electronic equipment are sometimes AC-powered, reducing the current that must be provided by the DC power supply. An induction motor generally tends to be heavier and less ef ficient than other types, and its speed limit im posed by the frequency of the AC power supply is a significant disadvantage.

A simple induction motor cannot provide the so phisticated control that is necessary in modern devices such as CD or DVD players, ink-jet printers, and scanners. A stepper motor, servo mo tor, and DC motors controlled with pulse-width modulation are preferable in these applications.

A reluctance motor may find applications in high- speed, high-end equipment including vacuum cleaners, fans, and pumps. Large variable reluctance motors, with high amperage ratings, may be used to power vehicles. Smaller variants are being used for power steering systems and wind shield wipers in some automobiles.

What Can Go Wrong

Compared with other devices that have moving parts, the brushless induction motor is one of the most reliable and efficient devices ever invented. However, there are many ways it can be dam aged. General problems affecting all types of motors are listed at “Heat effects” (page 188). Is sues relating specifically to AC motors are listed below.

Premature Restart

Large industrial three-phase induction motors can be damaged if power is reapplied before the motor has stopped rotating.

Frequent Restart

If a motor is stopped and started repeatedly, the heat that is generated during the initial surge of current is likely to be cumulative.

Undervoltage or Voltage Imbalance A voltage drop can cause the motor to draw more current than it is rated to handle. If this situation persists, overheating will result. Problems also

are caused in a three-phase motor where one

phase is not voltage-balanced with the others. The most common cause of this problem is an open circuit-breaker, wiring fault, or blown fuse affecting just one of the three conductors. The motor will try to run using the two conductors that are still providing power, but the result is likely to be destructive.

Stalled Motor

When power is applied to an induction motor, if the motor is prevented from turning, the con ductors in the rotor will carry a large current that is entirely dissipated as heat. This current surge will either burn out the motor or blow a fuse or circuit breaker. Care should be taken, in equip ment design, to minimize the risk that an induction motor may stall or jam.

Protective Relays

Sophisticated protective relays are available for industrial 3-phase motors, and can guard against all of the faults itemized above. Their details are outside the scope of this encyclopedia.

Excess Torque

As has been previously noted, the torque of an induction motor increases with the slip (speed difference) between the rotation of the magnetic field and the rotation of the rotor. Consequently, if the motor is overloaded and forced to run more slowly, it can deliver more rotational force. This can destroy other parts attached to the motor, such as drive belts.

Internal Breakage

An overloaded induction motor may suffer some cracking or breakage of its rotor. This may be ob vious because of reduced power output or vi bration, but can also be detected if the motor’s power consumption changes significantly.

DC motor What It Does,How It Works,Variants,Values,How to Use it,What Can Go Wrong

Posted on October 20, 2014 by Farahat Leave a comment

In this section, the term “traditional DC motor” is used to describe the oldest and simplest design, which consists of two brushes delivering power via a rotating, sectioned com mutate to two or more electromagnetic coils mounted on the motor shaft. Brushless DC motors (in which DC is actually converted to a pulse train) are also described here because “brushless DC” has become a commonly used phrase, and the motor is powered by direct current, even though this is modified internally via pulse-width modulation.

What It Does

A traditional DC motor uses direct current to cre ate magnetic force, which turns an output shaft. When the polarity of the DC voltage is reversed, the motor reverses its direction of rotation. Usu ally, the force created by the motor is equal in either direction.