READY AND THE WAIT STATE
As we mentioned earlier in this chapter, the READY input causes wait states for slower memory and I/O components. A wait state (Tw) is an extra clocking period, inserted between T2 and T3 to lengthen the bus cycle. If one wait state is inserted, then the memory access time, normally 460 ns with a 5 MHz clock, is lengthened by one clocking period (200 ns) to 660 ns.
In this section, we discuss the READY synchronization circuitry inside the 8284A clock generator, show how to insert one or more wait states selectively into the bus cycle, and examine the READY input and the synchronization times it requires.
The READY Input
The READY input is sampled at the end of T2 and again, if applicable, in the middle of Tw. If READY is a logic 0 at the end of T2, T3 is delayed and Tw is inserted between T2 and T3. READY is next sampled at the middle of Tw to determine whether the next state is Tw or T3. It is tested for a logic 0 on the 1-to-0 transition of the clock at the end of T2, and for a 1 on the 0-to-1 transition of the clock in the middle of Tw.
The READY input to the 8086/8088 has some stringent timing requirements. The timing diagram in Figure 9–14 shows READY causing one wait state (Tw), along with the required setup and hold times from the system clock. The timing requirement for this operation is met by the internal READY synchronization circuitry of the 8284A clock generator. When the 8284A is used for READY, the RDY (ready input to the 8284A) input occurs at the end of each T state.
RDY and the 8284A
RDY is the synchronized ready input to the 8284A clock generator. The timing diagram for this input is provided in Figure 9–15. Although it differs from the timing for the READY input to the
8086/8088, the internal 8284A circuitry guarantees the accuracy of the READY synchronization provided to the 8086/8088 microprocessors.
Figure 9–16 again depicts the internal structure of the 8284A. The bottom half of this diagram is the READY synchronization circuitry. At the leftmost side, the RDY1 and AEN1 inputs are ANDed, as are the RDY2 and AEN2 inputs. The outputs of the AND gates are then ORed to generate the input to the one or two stages of synchronization. In order to obtain a logic 1 at the inputs to the flip-flops, RDY1 ANDed with AEN1 must be active or RDY2 ANDed with AEN2 must be active.
The ASYNC input selects one stage of synchronization when it is a logic 1 and two stages when it is a logic 0. If one stage is selected, then the RDY signal is kept from reaching the 8086/8088 READY pin until the next negative edge of the clock. If two stages are selected, the first positive edge of the clock captures RDY in the first flip-flop. The output of this flip-flop is fed to the second flip-flop, so on the next negative edge of the clock, the second flip-flop captures RDY.
Figure 9–17 illustrates a circuit used to introduce almost any number of wait states for the 8086/8088 microprocessors. Here, an 8-bit serial shift register (74LS164) shifts a logic 0 for one or more clock periods from one of its Q outputs through to the RDY1 input of the 8284A. With appropriate strapping, this circuit can provide various numbers of wait states. Notice also how the shift register is cleared back to its starting point. The output of the register is forced high when the RD, WR, and INTA pins are all logic 1s. These three signals are high until state T2, so the shift register shifts for the first time when the positive edge of the T2 arrives. If one wait is desired, output QB is connected to the OR gate. If two waits are desired, output QC is connected, and so forth.
Notice in Figure 9–17 that this circuit does not always generate wait states. It is enabled from the memory only for memory devices that require the insertion of waits. If the selection signal from a memory device is a logic 0, the device is selected; then this circuit will generate a wait state.
Figure 9–18 illustrates the timing diagram for this shift register wait state generator when it is wired to insert one wait state. The timing diagram also illustrates the internal contents of the shift register’s flip-flops to present a more detailed view of its operation. In this example, one wait state is generated.
