EEPROM Data Memory
This is useful in applications where data read in at the ports or produced by the processor needs to be stored in non-volatile memory. For example, in a keypad-operated electronic lock, the lock code is entered by the user and then retained to be checked against user keypad input to release the lock. Data logging applications, where sampled input data may need to be retained over a period of time, may also need to store the data while the power is off. Electrically erasable programmable read-only memory (EEPROM), unlike flash ROM, can be written as individual data bytes, but is not as physically compact, so is provided in smaller blocks. EEPROM capacity ranges between 256 and 1k bytes, and is not fitted in some chips.
ALU and Working Registers
CISC processors tend to have a block of registers for storing current data, rather than a single working register (W) as found in the PIC. They also tend to have much larger address spaces. This means that the instructions, including operands, are typically 4 bytes in total, often more, compared with 14 bits for the PIC 16. An architecture with only one working register, used in conjunction with the RAM register block, reduces the overall number and complexity of instructions required, as the options are reduced. This does mean, however, that all data transfers must go through W. In the more powerful MCUs, the arithmetic and logic unit (ALU) support hardware can be more elaborate. For example, the 18F4580 has an 8 x 8 multiplier, but still has only one working register.
Stack Size
The stack size determines the number of subroutine or interrupt levels that can be used in the application program. A CISC processor can have an unlimited stack, as general purpose RAM is used, unlike the PIC, which has a dedicated internal stack of limited depth. The 12 series chips have only a two-level stack, the 16 series eight levels, and the 18 series 32 levels. This reflects the typical program complexity for each type. The application programmer needs to be aware of this limitation, and balance the advantages of a well-structured program using multiple subroutine levels, and the absolute limit imposed by the stack size. Unlike in CISC processors, the stack cannot be overwritten by a program instruction, making it more secure.