Spi peripheral
Context
● You are developing an embedded application using one or more members of the 8051 family of microcontrollers.
● The application has a time-triggered architecture, based on a scheduler.
● The microcontroller in your application will be interfaced to one or more peripher- als, such as a keypad, EEPROM, digital-to-analogue converter or similar device.
● Your microcontroller has hardware support for the SPI protocol.
Problem
Should you use the SPI bus to link your microcontroller to peripheral devices and, if so, how do you do so?
Background
There are five key features of SPI as far as the developer of embedded applications is concerned:
● SPI is a protocol designed to allow microcontrollers to be linked to a wide range of different peripherals – memory, displays, ADCs and similar devices – and requires (typically) three port pins for the bus, plus one chip-select pin per peripheral.
● There are many SPI-compatible peripherals available for purchase ‘off the shelf’.
● Increasing numbers of ‘Standard’ and ‘Extended’ 8051 devices have hardware sup- port for SPI and we will make use of such facilities in this pattern.
● A common set of software code may be used with all SPI peripherals.
● SPI is compatible with time-triggered architectures and, as implemented in this book, is faster than I2C (largely due to the use of on-chip hardware support). Typical data transfer rates will be up to 5,000–10,000 bytes / second (with a 1 ms scheduler tick).
We provide some background to SPI in this section.
History
Serial peripheral interface (SPI) was developed by Motorola and included on the 68HC11 and other microcontrollers. Recently, this interface standard has been adopted by manufacturers of other microcontrollers. Increasing numbers of ‘Standard’ and ‘Extended’ 8051 devices (see Chapter 3) have hardware support for SPI and we will make use of such facilities in this pattern.
Basic SPI operation
SPI is often referred to as a three-wire interface. In fact, almost all implementations require two data lines, a clock line, a chip select line (usually one per peripheral device) and a common ground: this is at least four lines, plus ground.
The data lines are referred to as MOSI (‘Master out Slave in’) and MISO (‘Master in Slave out’).
The overall operation of SPI is easy to understand if you remember that the proto- col is based on the use of two 8-bit shift registers, one in the Master, one in the Slave (Figure 24.1).
The key operation in SPI involves transferring a byte of data between the Master and the currently selected Slave device; simultaneously, a byte of data will be trans- ferred back from the Slave to the Master.
Single-Master, multi-Slave
SPI is a single-Master, multi-Slave interface. The Master generates the clock signal. As far as we are concerned here, the microcontroller will form the Master device and one or more peripheral devices will act as Slaves.
Choice of clock polarities
SPI supports two clock polarities. With polarity 0, the clock line is low in the quies- cent state: when active, the data to be sent are written on the rising clock edge and the data are read on the falling clock edge. With polarity 1, the clock line is high in the quiescent state: when active, the data to be sent are written on the falling clock edge and the data are read on the rising clock edge.
Polarity 0 is more widely used.
Maximum clock rate
The maximum clock rate for SPI is currently 2.1 MHz. Allowing for the fact that it takes eight clock cycles to transfer a byte of data and the fact that there are other overheads too (instructions and addresses, for example), the maximum data transfer rates will be around 130,000 bytes per second.
Microwire
Note that the Microwire interface standard (developed by National Semiconductor) is similar to SPI, although the connection names, polarities and other details vary: Microwire is not discussed further in this book.
Solution
Should you use SPI?
In order to determine whether use of an SPI bus is appropriate in your time-triggered application, we consider some key questions that should be asked when considering the use of any communications protocol or related technique.
Main application areas
Although the SPI bus may be used, for example, to connect processors (usually micro- controllers) to one another or to other computer systems, its main application area is – like I2C – in the connection of standard peripheral devices, such as LCD panels or EEPROMs to microcontrollers.
Ease of development
SPI can be used to communicate with a large number and range of peripherals. By using the same protocol to talk to a range of devices, development efforts may be reduced.
Scalability
Each SPI Slave device requires a separate /CS (chip select) line from the Master node. This increases the number of pins required on the microcontroller if large numbers of peripherals are used.
Flexibility
Individual SPI-compatible microcontrollers may act as Master or Slave nodes. We con- sider only the use of the microcontroller as the Master node in this pattern.
Speed of execution and size of code
The maximum clock rate for SPI is currently 2.1 MHz.
As we will be using hardware-based SPI in this pattern, the code overhead will be small.
Cost
The cost of licence fees for use of the bus is included in the cost of the peripheral components which you purchase: in most circumstances, there are no additional fees to pay.
Note that this may not be the case if, for example, you are implementing an SPI peripheral (to be sold for connection to an SPI bus). If in doubt, contact Motorola for further details.
Choice of implementations and vendors
The SPI library presented here may be used only with 8051 devices that have hard- ware support for SPI.
Suitability for use in time-triggered applications
As we saw in Chapter 18, the RS-232 communication protocol is appropriate for use in time-triggered applications. This suitability arises because the task duration associated with transmission (and reception) of data on an RS-232 network is very short. Note that this transmission time is not directly linked to the baud rate of the network, largely because almost all members of the 8051 family have on-chip hardware support for RS- 232, with the result that messages are transmitted and received ‘in the background’.
The situation with SPI is similar. Specifically, in this pattern, we are concerned with hardware-based SPI protocols. These typically impose a low software load and allow a short task duration. For example, if we consider the process of sending one byte of data to an SPI-based ROM chip (an example of this is presented in full later), then the total task duration is approximately 0.1 ms; note that this is considerably shorter than the equivalent operation using the I2C library presented in this book.
This task duration can be easily supported in a time-triggered application, even with 1 ms timer ticks.
How do you use SPI in a time-triggered application?
The discussions will centre around the Atmel AT89S53, a Standard 8051 device with on-chip SPI support. Note that hardware support provided by other manufacturers is very similar.
The AT89S53 SPI features include the following:
● Full-duplex, three-wire synchronous data transfer
● Master or Slave operation
● 1.5 MHz bit frequency (max.)
● LSB first or MSB first data transfer
● Four programmable bit rates
● End of transmission interrupt flag