QUESTIONS AND PROBLEMS
1. List the differences between the 8086 and the 8088 microprocessors.
2. Is the 8086/8088 TTL-compatible? Explain your answer.
3. What is the fan-out from the 8086/8088 to the following devices:
(a) 74XXX TTL
(b) 74ALSXXX TTL
(c) 74HCXXX CMOS
4. What information appears on the address/data bus of the 8088 while ALE is active?
5. What are the purposes of status bits S3 and S4?
6. What condition does a logic 0 on the 8086/8088 RD pin indicate?
7. Zxplain the operation of the TEST pin and the WAIT instruction.
8. Describe the signal that is applied to the CLK input pin of the 8086/8088 microprocessors.
9. What mode of operation is selected when MN>MX is grounded?
10. What does the WR strobe signal from the 8086/8088 indicate about the operation of the 8086/8088?
11. When does ALE float to its high-impedance state?
12. When DT>R is a logic 1, what condition does it indicate about the operation of the 8086/8088?
13. What happens when the HOLD input to the 8086/8088 is placed at its logic 1 level?
14. What three minimum mode 8086/8088 pins are decoded to discover whether the processor is halted?
15. Explain the operation of the LOCK pin.
16. What conditions do the QS1 and QS0 pins indicate about the 8086/8088?
17. What three housekeeping chores are provided by the 8284A clock generator?
18. By what factor does the 8284A clock generator divide the crystal oscillator’s output frequency?
19. If the F>C pin is placed at a logic 1 level, the crystal oscillator is disabled. Where is the timing input signal attached to the 8284A under this condition?
20. The PCLK output of the 8284A is MHz if the crystal oscillator is operating at 14 MHz.
The RES input to the 8284A is placed at a logic level in order to reset the 8086/8088.
22. Which bus connections on the 8086 microprocessor are typically demultiplexed?
23. Which bus connections on the 8088 microprocessor are typically demultiplexed?
24. Which TTL-integrated circuit is often used to demultiplex the buses on the 8086/8088?
25. What is the purpose of the demultiplexed BHE signal on the 8086 microprocessor?
26. Why are buffers often required in an 8086/8088-based system?
27. What 8086/8088 signal is used to select the direction of the data flows through the 74LS245 bidirectional bus buffer?
28. A bus cycle is equal to clocking periods.
29. If the CLK input to the 8086/8088 is 4 MHz, how long is one bus cycle?
30. What two 8086/8088 operations occur during a bus cycle?
31. How many MIPS is the 8086/8088 capable of obtaining when operated with a 10 MHz clock?
32. Briefly describe the purpose of each T state listed:
(a) T1
(b) T2
(c) T3
(d) T4
(e) Tw
33. How much time is allowed for memory access when the 8086/8088 is operated with a 5 MHz clock?
How wide is DEN if the 8088 is operated with a 5 MHz clock?
35. If the READY pin is grounded, it will introduce states into the bus cycle of the 8086/8088.
36. What does the ASYNC input to the 8284A accomplish?
37. What logic levels must be applied to AEN1 and RDY1 to obtain a logic 1 at the READY pin? (Assume that AEN2 is at a logic 1 level.)
38. Contrast minimum and maximum mode 8086/8088 operation.
39. What main function is provided by the 8288 bus controller when used with 8086/8088 maximum mode operation?