INTERFACING
�Multiplexed address-data bus lines are connected directly from the 8086 to 8087.
�The status lines and the queue status lines connected directly from 8086 to 8087.
�The Request/Grant signal RQ/GT0 of 8087 is connected to RQ/GT1 of 8086.
�BUSY signal 8087 is connected to TEST pin of 8086.
�Interrupt output INT of the 8087 to NMI input of 8086. This intimates an error condition.
�A WAIT instruction is passed to keep looking at its TEST pin, until it finds pin Low to indicates that the 8087 has completed the computation.
�SYNCHRONIZATION must be established between the processor and coprocessor in two situations.
a) The execution of an ESC instruction that require the participation of the NUE must not be initiated if the NUE has not completed the execution of the previous instruction.
b) When a processor instruction accesses a memory location that is an operand of a previous coprocessor instruction .In this case CPU must synchronize with NPX to ensure that it has completed its instruction.
Processor WAIT instruction is provided.
Exception Handling
�The 8087 detects six different types of exception conditions that occur during instruction execution. These will cause an interrupt if unmasked and interrupts are enabled.
1)INVALID OPERATION
2)OVERFLOW
3)ZERO DIVISOR
4)UNDERFLOW
5) DENORMALIZED OPERAND
6) INEXACT RESULT