6.3 Case Study: The VHDL Hardware Description Language
In this section we present a brief overview of VHDL (VHSIC Hardware
Description Language, in which VHSIC is yet another acronym for Very High Speed Integrated Circuit). Hardware description languages (HDLs), like VHDL and AHPL, are languages used for describing computer hardware, focusing primarily on logic devices and IC design. In the case of VHDL, however, designs can be specified at many different levels. For example, the control unit implemented in this chapter could be specified in VHDL.
We first cover the background that led to the development of VHDL, and then describe some of its properties. We then take a look at a VHDL specification of the majority function.
6.3.1 BACKGROUND
VHDL was the result of a collaboration between the Department of Defense (DOD), and many US industries. DOD, primarily through its Defense Advanced Research Products Agency (DARPA), realized in the late 1970’s that IC design and fabrication was becoming so complex that a set of integrated design tools was needed for both design and simulation. It was felt that the tools should allow the user to specify a circuit or system from the highest, or behavioral level down to the lowest levels of actual IC layout and design, and further- more, all of these specifications should be verifiable by simulators and other rule checkers.
The first preliminary requirements definition for the language was issued by DOD in 1981, as a recognition of the need for a more consistent approach to computer hardware design. The contract for the first version of the language was won by a consortium of IBM, Texas Instruments, and Intermetrics, a software engineering firm specializing in programming language design and implementation.
The consortium released a preliminary version for testing and comment in 1985. An updated version was submitted to the IEEE for standardization in 1986, the result being named IEEE 1076-1987. In 1993, a newer version, IEEE 1076-1993, was approved that addressed a number of minor problems and added several new features.
By almost any measure VHDL is a success, with many users both inside and out- side the defense contractor community. DOD now requires that all Applica- tion-Specific Integrated Circuits (ASICs) be accompanied by their VHDL model for checking and simulation. Almost all CAD vendors now support VHDL in their toolsets.
6.3.2 WHAT IS VHDL?
In its most basic terms VHDL is a hardware description language that can be used to describe and model digital systems. VHDL has an inherent sense of time, and can manage the progression of events through time. Unlike most procedural languages that are in common use, VHDL supports concurrent execution, and is event driven.
Concurrent execution
Concurrent execution means that unless special efforts are taken to specify sequential execution, all of the statements in a VHDL specification are executed in parallel. This is the way it should be, since when power is applied to a digital system the system runs “in parallel.” That is, current flows through circuits according to the rules of physics and logic, without any inherent sense of “which came first.”
Event-driven systems
VHDL deals with signals propagating through digital systems, and therefore log- ically and naturally supports the concept of changes in state as a function of time. Having a sense of time, it supports concepts such as “after,” “until,” and “wait.” As an event-driven system, it begins execution by executing any initialization code, and then records all changes in signal values, from 0®1 and 1®0, occur- ring at the inputs and outputs of components. It records these changes, or events, in a time-ordered queue, known as the event queue. It examines these events and if an event has an effect upon some component, that effect is evaluated. If the effect causes further events to take place the simulator likewise places these new events in the event queue, and the process continues until and unless there are no further events to process.
Levels of abstraction, and hierarchical decomposition
As mentioned above, VHDL specifications can be written at almost any level of abstraction from the purely algorithmic level, where behavior is specified by for- mal algorithms, to the logic level, where behavior is specified by Boolean expressions.
Furthermore, a VHDL specification may be composed of a hierarchy of components, that is, components may contain components, which may themselves contain components. This models the physical world, where, for example, a motherboard may contain IC chips, which are composed of modules, which are in turn composed of sub-modules, all the way down to individual logic gates, and finally transistors.
6.3.3 A VHDL SPECIFICATION OF THE MAJORITY FUNCTION
Let us explore how VHDL can be used to implement a small digital component by examining several implementations of the majority function, which produces a 1 at its output when more than half of its inputs are 1, otherwise it produces a 0 at its output. This is a useful function for fault tolerance, in which multiple systems that perform the same operations on the same data set “vote,” and if one of the systems deviates from the others, its output is effectively ignored. The majority function is discussed in detail in Appendix A. Its truth table is shown in Figure A-15 and Figure A-16, reproduced here as Figure 6-25.
In VHDL the specification of any component such as the majority function is split into two parts, an entity part and an architecture part. These correspond roughly to the syntactic and semantic parts of a language specification: the entity part describes the interface of the component without saying anything about its internal structure. The architecture part describes the internal behavior of the component. Here is an entity specification for the 3-input majority function:
Interface specification for the majority component
Keywords are shown in bold, and comments begin with “–” and end at the end of the line. Statements are separated by semicolons, “;”.
The entity specification describes just the “black box” input and output sig- nals in Figure 6-25c. The port declaration describes the kind of signals going into and out of the entity. Port modes include in for signals that flow into the entity, out for signals that flow out of the entity, and inout for bidirectional signals. There are also several other special purpose port modes.
With the interface to the majority component specified we can now model the internal functioning of the component, using the architecture specification:
Behavioral model for the majority component
This model describes the relationship between the entity declaration of MAJOR- ITY and the architecture of MAJORITY. The names A_IN, B_IN, C_IN, and F_OUT in the architecture model must match the names used in the entity declaration.
This kind of architectural specification is referred to as a behavioral one, since it defines the input/output function by specifying an explicit transfer function. That function is a Boolean expression that implements the Boolean function shown in Figure 6-25a,b. Notice, however, that even at this level of specification
that we can include a time delay between inputs and outputs, using the after keyword. In this case, the event computing the value of F_OUT will be triggered 4 ns after a change in any of the input values.
It is also possible to specify the architecture at a level closer to the hardware by specifying logic gates instead of logic equations. This is referred to as a structural model. Here is such a specification:
Structural model for the majority component
In generating a structural model for the MAJORITY entity we will follow the gate design given in Figure 6-25b. We begin the model by describing a collection of logic operators, in a special construct of VHDL known as a package. The package is assumed to be stored in a working library called WORK. Following the package specification we repeat the entity declaration, and then, using the package and entity declarations we specify the internal workings of the majority component by specifying the architecture at a structural level:
The package declaration supplies three gates, a 3-input AND gate, AND3, a 4-input OR gate, OR4, and a NOT gate, NOT1. The architectures of these gates are assumed to be declared elsewhere in the package. The entity declaration is unchanged, as we would expect, since it specifies MAJORITY as a “black box.”
The body specification begins with a use clause, which imports all of the declarations in the LOGIC_GATES package within the WORK library. The signal declaration declares seven BIT signals that will be used internally. These signals are used to interconnect the components within the architecture.
The instantiations of the three NOT gates follow, NOT_1, NOT_2, and NOT_3, all of which are NOT1 gates, and the mapping of their input and out- put signals are specified, following the port map keywords. Signals at the inputs and outputs of the logic gates are mapped according to the order in which they were declared within the package.
The rest of the body specification connects the NOT gates, the AND gates, and the OR gate together as shown in Figure 6-25b.
Notice that this form of architecture specification separates the design and implementation of the logic gates from the design of the MAJORITY entity. It would be possible to have several different implementations of the logic gates in different packages, and to use any one of them by merely changing the uses clause.
6.3.4 9-VALUE LOGIC SYSTEM
This brief treatment of VHDL only gives a small taste of the scope and power of the language. The full language contains capabilities to specify clock signals and various timing mechanisms, sequential processes, and several different kinds of signals. There is an IEEE standard 9-value logic system, known as STD_ULOGIC, IEEE 1164-1993. It has the following logic values:
Without getting into too much detail, these values allow the user to detect logic flaws within a design, and to follow the propagation of uninitialized or weak signals through the design.