Questions
Find the following using the information provided in Chapter 2.
1. Size of the internal RAM.
2. Internal ROM size in the 8031.
3. Execution time of a single byte instruction for a 6 megahertz crystal.
4. The 16-bit data addressing registers and their functions.
5. Registers that can do division.
6. The flags that are stored in the PSW.
7. Which register holds the serial data interrupt bits TI and RI.
8. Address of the stack when the 8051 is reset.
9. Number of register banks and their addresses.
10. Ports used for external memory access.
11. The bits that determine timer modes and the register that holds these bits.
12. Address of a subroutine that handles a timer 1 interrupt.
13. Why a low-address byte latch for external memory is needed.
14. How an 1/0 pin can be both an input and output.
15. Which port has no alternate functions.
16. The maximum pulse rate that can be counted on pin T1 if the oscillator frequency is 6 megahertz.
17. Which bits in which registers must be set to give the serial data interrupt the highest
priority.
18. The baud rate for the serial port in mode 0 for a 6 megahertz crystal.
19. The largest possible time delay for a timer in mode I if a 6 megahertz crystal is used.
20. The setting of TH1. in timer mode 2, to generate a baud rate of 1200 if the serial port is in mode I and an 11.059 megahertz crystal is in use. Find the setting for both values of SMOD.
21. The address of the PCON special-function register.
22. The time it will take a timer in mode I to overflow if initially set to 03AEh with a 6 megahertz crystal.
23. Which bits in which registers must be set to 1 to have timer 0 count input pulses on pin
T0 in timer mode 0.
24. The register containing GF0 and GF1.
25. The signal that reads external ROM.
26. When used in multiprocessing. which bit in which register is used by a transmitting 8051 to signal receiving 805’s that an interrupt should be generated.
27. The two conditions under which program opcodes are fetched from external, rather than internal, memory.
28. Which bits in which register(s) must be set to make (INTO)’ level activated, and (INT1)’ edge triggered.
29. The address of the interrupt program for the (INTO)’ level-generated interrupt.
30. The bit address of bit 4 of RAM byte 2Ah.