The Cutler-Hammer company system uses the English logic ap proach which is covered in previous chapters . The purpose of this chapter is to present the details of this system as they apply to and modify material in previous chapters.
The material for this chapter was furnished by the Cutler Hammer company.1
12 ·1 CUTLER-HAMMER SIGNAL CONVERTERS
We have seen that the function of the signal converter is to convert the higher-voltage pilot signal to a reduced d-e voltage suitable for the input of static logic circuitry. Two basic types of signal converters are commonly used to perform this function; thus a choice of the type of voltage to be applied to the pilot device is available.
1 SOURCE: Cutler-Hammer, Inc., “DSL Application s Manual,” 2d ed .,Aug. 1, 1965.
The D-C Resistor Type ( Fig. 12·1). This signal converter op erates from 48-volts d-e supplied by the power supply. It is suitable for most pilot devices, provided that the contacts have good “wipe” and are subject to frequent use.
The A-C Transformer Type (Fig. 12·2). This type of signal converter utilizes 115 volts a-c across the monitored contacts, and then uses voltage, when present, to produce a 10-volt d-e output signal to the logic. It is recommended, because of its greater energy level, where pilot devices are located in contami nated atmospheres or subject to infrequent use.
The d-e signal converter with a push-button pilot device and typical static switch dotted in is illustrated in Fig. 12·1. When push button PB is closed, current flows through resistors R 1 and R2, which serve as a voltage divider. Note that the lamp functions both as R 1 and as a state light. The purpose of the resistors is to reduce the 48 volts, in this case to voltage that is compatible with static logic circuitry. This voltage comes from the drop across R2 and appears at point A. It is, therefore, the input signal to the following logic element. Incidentally, the output of any signal converter can be regarded as a voltage at a given point (A in our illustration) which can be sensed by a static switch.
With the push button closed, the voltage that appears across R2 must be the same as that impressed across the 10-volt buses. Were this not the case, lost signals could result. Yet the voltage dividing circuit is designed to present a slightly greater voltage than 10 volts across resistor R2. Here is the reason for what may appear an inconsistency. Should the bus voltages drift and cause the signal converter to present a slightly higher than 10-volt signal, the voltage can always be “pulled down” to the desired value. But should the signal voltage go below 10 volts, voltage cannor be added to provide the necessary amount. The clamping diode D performs this function of maintaining a uni form drop across R2 by “bleeding off” the excess voltage. The
final result is a signal converter that provides protection from voltage drift.
The a-c transformer-type signal converter (Fig. 12·2) both reduces and rectifies the 115-volt a-c signal voltage to the low d-e voltage required by the logic circuitry. Note that the pilot device, push button PB, is in series with the 115-volt primary of the transformer. The latter steps down the voltage. The rec tifiers D l and D2 plus the transformer produce a full-wave direct current which is filtered by capacitor C. This filtered d-e voltage output is applied to the voltage-dividing resistors R 1 and R2.
Diode D3, which is connected to the +10-volt bus, passes current whenever the junction of R 1 and R2 attempts to go above the power-supply level. This clamping action keeps the signal level at the same voltage as the power supply fed to the static devices, i.e., 10 volts. It should be noted that when current bleeds off through D3, the return path is through the connection at point B . The lamp labeled R 1 again functions both as a resis tor and as a state light.
12·2 STATIC LOGIC ELEMENTS
This section contains the basic building blocks of a control sys tem-namely, the static switches. The elements will be covered
one by one in detail, and how and why they work the way they do will be explained.
The AND switch is a device which produces an output only when every input is energized. When all three inputs are energized with a +10-volt signal, the output will be 10 volts.
Let us consider the circuit of Fig. 12·3 with all push buttons open (PB 1 only shown). No input signal can then appear at any one of the input points A 1, A 2, and A 3. This no-input condition permits current to flow through the entire series-paral lel voltage-dividing network, consisting of resistors R 1 to R7. Of special significance is resistor R7, since the voltage drop
across it also appears across the emitter-base circuit of transistor TI. Its base, therefore, is held sufficiently negative to cause base current to flow from E to B in T 1 and through resistors R 1 to R6. As we have seen earlier, base current causes conduction in the power circuit. Therefore T1 conducts, bringing a+ 10-volt potential to point C. With point C at + 10 volts, the base path of transistor T2 is blocked, causing this transistor to assume its nonconducting or open state. The final result is that point
D. the output terminal, is connected only to the 0-volt bus and exhibits its no-output condition. When there is no input signal, there is no output signal.
Push Button PB I Closed, PB2 and PB3 Open. With push but ton PB I closed, one signal input is present; i.e., the signal converter presents +10 volts to point A 1. This condition may be regarded as blocking the right-hand leg of the voltage-dividing network. But current still flows through resistor R?, which still holds point B sufficiently negative to permit base current to flow through transistor T1 and the remaining two resistor legs. Therefore, transistor T1 maintains its conducting or ON state, while transistor T2 maintains its nonconducting or OFF state. The “ali-or-nothing” concept of the AND switch is demonstrated; that is, one of a given number of inputs to an AND switch cannot, when energized, give an output.
Push Buttons PB 1 and PB2 Closed, PB3 Open. With the clos ing of push button PB2 (not shown), another input is energized,
bringing point A 2 to +10 volts potential. Now current in the second or middle leg of the voltage-dividing network is blocked. But the voltage drop across R7 still holds the base of transistor T I negative. Therefore, base current still flows through T I, this time through the remaining leg of the voltage-dividing network . Transistor T I still stays on, and transistor T2 still stays off. The all-or-nothing requirement of the AND switch remains intact. Two out of three energized inputs are not enough to turn on the AND switch.
Push Buttons PBl, PB2, and PB3 Closed. The closing of push button PB3 brings point A3 to +10 volts. Now with points A 1, A 2, and A 3 all at +10 volts, point B too is at 10 volts. Therefore, current can no longer flow from emitter to base of transistor T 1. The absence of base current, as we have seen, is equivalent to nonconduction in the power circuit. As a result, point C goes negative, permitting T2 base current through T2 and R8. Now transistor T2 conducts, turning on the state-indica tion light and producing a +10-volt output signal at point D.
The aU-or-nothing concept of the AND switch is realized. With all inputs energized, an output appears.
Should the application not require the full input capabilities of the AND switch, the unused terminals must be connected to the +10-volt bus.
The OR switch (Fig. 12 ·4) can be likened to relay contacts connected in parallel. Therefore, whenever any one of the three inputs is energized with a +10-volt signal, a +10-volt output
will appear. Note that the OR switch diagram is similar to the AND switch, with this exception: the resistors have been replaced with rectifiers.
With push button PB 1 or either of the other two push buttons closed, the appropriate points A 1, A 2, and A 3 will receive a +10 volt signal. Therefore, base current cannot flow through transistor T 1. As a consequence, transistor Tl is shut off, and, as we have seen before, transistor T2 is turned on. An output appears at point P.
The diodes D 1, D2, and D3 prevent unwanted feedback. That is, they prevent a feedback circuit from one input to the state indication light of preceding logic units that may be driving the OR switch. Such feedback could cause false state indication.
The NOT switch (Fig. 12·5) is a device that produces an output only when the input is not energized. But when an input does exist, no output appears. The relay equivalent of a NOT
switch is a single-pole relay with a normally closed contact and one input signal to the coil. The purpose of the NOT switch is to provide signal inversion where that function is not only desirable but necessary. The NOT switch operates with either an input present or an input absent. The following are descriptions of how the switch works in each of these conditions.
Case 1: Input Present. With push button PB closed a +IO volt input signal appears at point l. Current will therefore flow from the base to the emitter of transistor Tl and through R2 to the negative side of the line, causing Tl to conduct. Note that transistor T1 is an NPN rather than the PNP type. Note also that the arrow points away from the base, indicating that current flows from base to emitter. Now with transistor Tl conducting, the junction of diode D 1 and R2 is at +10 volts; T2 cannot conduct, and there can be no output signal. An input results in no output.
Case 2: Input Absent. With push button PB open, no +10- volt input signal appears at point I. Therefore, the emitter of transistor Tl will not be at + 10 volts. Now current can flow from the emitter of transistor T2 to its base, through D 1 and R2.
Transistor T2 can now conduct and supply a + 10-volt output.
No input results in an output.
The primary purpose of the retentive MEMORY (Fig. 12 ·6) is to provide power-loss memory . This is accomplished by a two-coil magnetically latching reed relay which operates simi larly to the conventional latched relay. In the retentive MEMORY, however, each reed coil is driven by its own logic-performing transistors.
An input signal at either A or B will block one leg of the AND function associated with transistor Tl. + 10 volts applied to the inhibit terminal/ will block the other leg. Tl , thus denied a base-current path, shuts off, turning on T2. T2 energizes the reed-relay coil C1, closing the reed contact. Terminal E is the output terminal.
Inputs C and D, in combination with the same inhibit terminal, function similarly through T3 and T4, except that they cause the reed contact to open. Discharge diodes are provided on both coil circuits.
The set and reset inputs, one associated with A and B, the other with C and D, represent points on the front of the boards. These allow for manual setting of the reed position with a probe
connected to the positive side of the 10-volt supply. Only a momentary signal is necessary to either set or reset the unit.
The inhibit terminal is a master terminal, and as such this one terminal can inhibit the set and reset functions of both switches on the board. If this terminal is not used for logic
purposes, it should be tied to either the +10-volt bus or the
special reset gate described later .
The set-reset MEMORY (Fig. 12·7) performs a simple memory
function. A momentary input signal, +10 volts, if applied to the
set terminal, produces an output signal; if the input signal is
applied to the reset terminal , it shuts the switch off . The master reset terminal, which serves all switches on the board, should be connected to the reset gate circuit described later. This will insure that the set-reset MEMORY will assume the no-output con dition when power comes on.
If the no-output state is present, transistor T2 will be conducting. Its base-current path uses diode Dl and resistor R8. In the manner we have seen before, the conducting state of T2 will block T3 base current, holding T3 off. Tl will also be conducting, with its base-current path through R 1 and some other logic unit’s load resistor. This is essential, as it blocks the R4R5 base-current path of T2 so that terminals B or C can set the unit.
A setting input calls for either B or C to be driven to +10 volts by the output signal of some other logic unit. This shuts off T2 base current. T2 turns off. T3 turns on, the output signal appears, and the T2 base-current path through R8 is blocked. The set signal may now be removed. To reset the unit, terminal A is driven to +10 volts. T1 shuts off. T2 base current appears in R4 and R5, turning T2 on and T3 off. T2 base current returns to the path D1R8. The reset signal may now be removed. When the 10-volt power first ap pears , all the transistors start to turn on. The master reset termi nal, held negative by the reset gate, insures that T2 has a base current path and ends up conducting.
The duo-delay timer (Fig. 12·8) is an adjustable, multirange timer. Range selection (0 to 1 minute maximum) is achieved · by the addition of external capacitors. A board-mounted poten tiometer provides for adjustment. Three modes of operation are possible by varying the external connections to the board. The E timer provides time-delay after energization. The D timer pro vides time-delay after deenergization. There is also a combina tion E and D timer.
Connecting jumper A from the input terminal to the terminal which is associated with diode D 1 provides an E timer. Jumper B from the input terminal to the terminal associated with diode
D2 yields the D timer. Omission of both jumpers produce s a combination E and D timer. Only the E timer operation will be discussed.
Transistors T1 and T2 operate as a multivibrator or oscillator. If one assumes T2 is conducting, its base-current path includes capacitor C1 and resistor R 1 to reach the negative side of the line. As we have seen before, the presence of T2 base current means that T2 assumes the conducting state. This provides a +10-volt output to the RC pulse-length circuit and also holds off T1 by blocking its base current at the junction C2R4. As T2 continues to conduct, its base current causes C 1 to take on a charge. The charging of C1 starts to produce an increasing impedance to T2 base current, which starts to shut off T2 power circuit. The shutting off of T2 causes the voltage at C2R4 to drop, which permits T1 base current to start turning on the T1 power circuit. T1 and T2 will continue to alternate as long as the 10-volt supply is connected to the board. The output of the oscillator, the + 10-volt signal from T2, is fed to the RC circuit C3R5 where pulse length is established. Transistor T3 of the pulse generator is controlled by the pulses from the pulse-length circuit. In a manner we have seen before, T4 inverts the signal from T3. T4 thus produces +10-volt pulses at a fre quency set by the oscillator and of a length set by the RC pulse length circuit. These pulses are sent to both timing circuits on the board. The capacitor C6, which may be paralleled externally by C5, determines the time range. The variable resistor P1 con trols the discharge of the capacitor in theE timer.
If one assumes that the input terminal is tied to some other logic circuit, its output load resistor provides a path to the nega tive bus, and its transistor a path to the positive bus. If we assume no input signal, C6 charges. The path is: positive bus, C6, D1, and through jumper A to the input terminal. The timer is now reset.
When an input signal appears, both sides of C6 are connected to the positive bus. C6 starts to lose its charge through the input terminal which is externally connected to the positive bus, R 11,
and Pl. Pl controls the rate. As C6 discharges, point X is driven more positive.
The next event occurs when C6 has sufficiently discharged to permit C7 to charge with point X positive. If we assume that C7 charges with point X approaching +10 volts while T4 is not conducting, then when T4 starts conducting, the negative side of C7 will be driven to + 10 volts. This causes point X to go to +20 volts. C7 discharges through diode D3, interrupt ing T5 base-current path R 15 and R 16. T5 shuts off. T6 thus starts conducting, providing an output signal and blocking T5 base current. The output signal will remain until the input signal is removed. This stops the positive pulses from C7 and allows T5 base current to use R12 and R6. T5 then turns on, and shuts off T6.
The D timer operates similarly, except that jumper B, hence diode D2, controls C6 holding discharged when the input is at +10 volts. C6 is forced to charge through P 1 after the input signal is removed. This delays removal of the output signal, as C7 can only generate pulses when C6 is discharged.
Note that terminal R, associated with transistor T4, when held at zero volts as power is applied, allows the timing capacitor to charge. This prepares the timer for normal operation, and terminal R is properly called a master reset terminal. It should be connected to a reset gate as described later.