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Why additional processors may not always improve reliability It is very important to appreciate that – without due care – increasing the numbers of processors in a network can have a detrimental impact on overall system reliability. It is not difficult to see why this is the case. For example, we will ignore the possibility […]
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How do we link more than one processor? We will now begin to consider some of the challenges that face developers who wish to design multiprocessor applications. We begin with a fundamental problem: ● How do we keep the clocks on the various nodes synchronized? We then go on to address two further problems that […]
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The benefits of modular design Suppose we are required to produce a range of different clocks, with various forms of display (Figure 25.2). Some of the clocks may have different features (for example, the ability to set an alarm), but the key tasks are the same in all cases: to keep accurate track of the […]
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In this chapter, we consider one additional important characteristic of embedded applications: the use of multiple processors. As we will see, the scheduler architecture introduced in previous chapters may be extended without difficulty in order to support such applications. Introduction Despite the diverse nature of the embedded applications we have discussed in previous chapters, each […]
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Example: Using an SPI EEPROM (X25320 or similar) In this example we present an SPI library allowing communication with an external EEPROM. In this case we have used a X25320 (4k × 8-bit) device, but any similar SPI EEPROM can be used without difficulty. Such devices are very useful as a means of storing non-volatile […]
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Time-triggered architectures for multiprocessor systems In Part F, we turn our attention to multiprocessor applications. As we will see, an important advantage of the time-triggered (co-operative) scheduling architecture is that it is inherently scaleable and that its use extends naturally to multiprocessor environments. In Chapter 25, we consider some of the advantages – and disadvantages […]
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Example: SPI core library Our SPI implementation consists of an SPI ‘core’, to which additional libraries are added to match the needs of particular EEPROMs etc.
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Hardware resource implications With on-chip hardware support, SPI PERIPHERAL imposes a minimal software load. Reliability and safety issues The SPI protocol incorporates only minimal error-checking mechanisms: detection of data corruption (for example) during the transfer of information to or from a periph- eral device must be carried out in software, if required. Portability This pattern […]
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Spi peripheral Context ● You are developing an embedded application using one or more members of the 8051 family of microcontrollers. ● The application has a time-triggered architecture, based on a scheduler. ● The microcontroller in your application will be interfaced to one or more peripher- als, such as a keypad, EEPROM, digital-to-analogue converter or […]
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Project header Context ● You are developing an embedded application using one or more members of the 8051 family of microcontrollers. ● You are designing an appropriate software foundation for your application. Problem How do you group together all the information relating to the hardware platform used in your project? Background — Solution As we […]
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