MEMORY:The Memory Hierarchy and Random Access Memory.

MEMORY In the past few decades, CPU processing speed as measured by the number of instructions executed per second has doubled every 18 months, for the same price. Computer memory has experienced a similar increase along a different dimension, quadrupling in size every 36 months, for the same price. Memory speed, however, has only increased […]
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Summary of data path and control.

■ SUMMARY A microarchitecture consists of a data path and a control section. The data path contains data registers, an ALU, and the connections among them. The control section contains registers for microinstructions (for a microprogramming approach) and for condition codes, and a controller. The controller can be micro- programmed or hardwired. A micro programmed […]
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Data path and control: case study: the vhdl hardware description language (background, what is vhdl?, a vhdl specification of the majority function and 9-value logic system).

6.3 Case Study: The VHDL Hardware Description Language In this section we present a brief overview of VHDL (VHSIC Hardware Description Language, in which VHSIC is yet another acronym for Very High Speed Integrated Circuit). Hardware description languages (HDLs), like VHDL and AHPL, are languages used for describing computer hardware, focusing primarily on logic devices […]
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Data path and control: hardwired control.

Hardwired Control An alternative approach to a micro programmed control unit is to use a hard- wired approach, in which a direct implementation is created using flip-flops and logic gates, instead of using a control store and a microword selection mechanism. States in a finite state machine replace steps in the microprogram. In order to […]
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Data path and control: a micro architecture for the arc (timing, developing the micro program, traps and interrupts and nanoprogramming).

TIMING The microarchitecture operates on a two-phase clock cycle, in which the master sections of all of the registers change on the rising edge of the clock and the slave sections change on the falling edge of the clock as shown in Figure 6-14. All of the registers use falling edge-triggered master/slave D flip-flops except […]
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Data path and control: a micro architecture for the arc (the data path and the control section).

6.1 A Micro architecture for the ARC In this section we consider a micro programmed approach for designing the ARC control unit. We begin by describing the data path and its associated control signals. The instruction set and instruction format for the ARC subset is repeated from Chapter 4 in Figure 6-2. There are 15 […]
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Datapath and control : basic s of the microarchitecture

DATAPATH AND CONTROL In the earlier chapters, we examined the computer at the Application Level, the High Level Language level, and the Assembly Language level (as shown in Figure 1-4.) In Chapter 4 we introduced the concept of an ISA: an instruction set that effects operations on registers and memory. In this chapter, we explore […]
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Summary of languages and the machine

■ SUMMARY A high level programming language like C or Pascal allows the low-level architecture of a computer to be treated as an abstraction. An assembly language program, on the other hand, takes a form that is very dependent on the underlying architecture. The instruction set architecture (ISA) is made visible to the programmer, who […]
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Languages and the machine: case study: extensions to the instruction set – the intel mm x™ and motorola altivec simd instructions (background, the base architectures, vector registers, vector arithmetic operations, vector compare operations and case study summary).

Case Study: Extensions to the Instruction Set – The Intel MM X™ and Motorola AltiVec SIM Dinstructions. As integrated circuit technology provides ever increasing capacity within the processor, processor vendors search for new ways to use that capacity. One way that both Intel and Motorola capitalized on the additional capacity was to extend their ISAs […]
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