An introduction to schedulers:Co-operative and pre-emptive scheduling

Co-operative and pre-emptive scheduling We have discussed in very general terms the use of a scheduler to execute functions at particular times. Before we begin to consider the creation and use of a scheduler in detail in the next chapter, we need to appreciate that there are two broad classes of scheduler: ● The co-operative […]
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An introduction to schedulers:A closer look at pre-emptive schedulers

A closer look at pre-emptive schedulers The discussion in this section is more technical than the previous sections in this chapter and may be omitted on a first reading of the book. Various research studies have demonstrated that, compared to pre-emptive schedulers, co-operative schedulers have a number of desirable features. For example, Nissanke (1997, p. […]
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Co-operative schedulers

Introduction In this chapter, we discuss techniques for creating co-operative schedulers suitable for use in single-processor environments. These provide a very flexible and predictable software platform for a wide range of embedded applications, from the simplest con- sumer gadget up to and including aircraft control systems. The following pattern is presented in this chapter: ● […]
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An introduction to schedulers:Executing multiple tasks at different time intervals

Executing multiple tasks at different time intervals While the great majority of embedded systems are required to run only one pro- gram, they do need to run multiple tasks (implemented as ‘C’ functions in this book): these tasks must, as mentioned earlier, run on a periodic or one-shot basis. These tasks will typically have different […]
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An introduction to schedulers:Assessing the Super Loop architecture

Assessing the Super Loop architecture Many of the features of the modern desktop OS, such as graphics capability, printing and disk access, are of little value in embedded applications, where sophisticated graphics screens, printers and disks are unavailable. As a result, as we saw in Chapter 9, the software architecture used in many simple embedded […]
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QUESTIONS AND PROBLEMS ON THE PENTIUM II, PENTIUM III, PENTIUM 4, AND CORE2 MICROPROCESSORS.

QUESTIONS AND PROBLEMS 1. What is the size of the level 1 cache in the Pentium II microprocessor? 2. What sizes are available for the level 2 cache in the Pentium II microprocessor? (List all versions.) 3. What is the difference between the level 2 cache on the Pentium-based system and the Pentium II-based system? […]
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