String Manipulation Instructions
A series of data byte or word available in memory at consecutive locations, to be referred as Byte String or Word String. A String of characters may be located in consecutive memory locations, where each character may be represented by its ASCII equivalent.
The 8086 supports a set of more powerful instructions for string manipulations for referring to a string, two parameters are required.
I. Starting and End Address of the String.
II. Length of the String.
The length of the string is usually stored as count in the CX register.The incrementing or decrementing of the pointer, in string instructions, depends upon the Direction Flag (DF) Status. If it is a Byte string operation, the index registers are updated by one. On the other hand, if it is a word string operation, the index registers are updated by two.
REP : Repeat Instruction Prefix
This instruction is used as a prefix to other instructions, the instruction to which the REP prefix is provided, is executed repeatedly until the CX register becomes zero (at each iteration CX is automatically decremented by one).
i. REPE / REPZ – repeat operation while equal / zero.
ii. REPNE / REPNZ – repeat operation while not equal / not zero.
These are used for CMPS, SCAS instructions only, as instruction prefixes.
MOVSB / MOVSW :Move String Byte or String Word
Suppose a string of bytes stored in a set of consecutive memory locations is to be moved to another set of destination locations.The starting byte of source string is located in the memory location whose address may be computed using SI (Source Index) and DS (Data Segment) contents.
The starting address of the destination locations where this string has to be relocated is given by DI (Destination Index) and ES (Extra Segment) contents.
CMPS : Compare String Byte or String Word
The CMPS instruction can be used to compare two strings of byte or words. The length of the string must be stored in the register CX. If both the byte or word strings are equal, zero Flag is set.
The REP instruction Prefix is used to repeat the operation till CX (counter) becomes zero or the condition specified by the REP Prefix is False.
SCAN : Scan String Byte or String Word
This instruction scans a string of bytes or words for an operand byte or word specified in the register AL or AX. The String is pointed to by ES:DI register pair. The length of the string s stored in CX. The DF controls the mode for scanning of the string. Whenever a match to the specified operand, is found in the string, execution stops and the zero Flag is set. If no match is found, the zero flag is reset.
LODS : Load String Byte or String Word
The LODS instruction loads the AL / AX register by the content of a string pointed to by DS : SI register pair. The SI is modified automatically depending upon DF, If it is a byte transfer (LODSB), the SI is modified by one and if it is a word transfer (LODSW), the SI is modified by two. No other Flags are affected by this instruction.
STOS : Store String Byte or String Word
The STOS instruction Stores the AL / AX register contents to a location in the string pointer by ES : DI register pair. The DI is modified accordingly, No Flags are affected by this instruction.
The direction Flag controls the String instruction execution, The source index SI and Destination Index DI are modified after each iteration automatically. If DF=1, then the execution follows autodecrement mode, SI and DI are decremented automatically after each iteration. If DF=0, then the execution follows autoincrement mode. In this mode, SI and DI are incremented automatically after each iteration.
Flag Manipulation and a Processor Control Instructions
These instructions control the functioning of the available hardware inside the processor chip. These instructions are categorized into two types:
1. Flag Manipulation instructions.
2. Machine Control instructions.
Flag Manipulation instructions
The Flag manipulation instructions directly modify some of the Flags of 8086.
i. CLC – Clear Carry Flag.
ii. CMC – Complement Carry Flag.
iii. STC – Set Carry Flag.
iv. CLD – Clear Direction Flag.
v. STD – Set Direction Flag.
vi. CLI – Clear Interrupt Flag.
vii. STI – Set Interrupt Flag.
Machine Control instructions
The Machine control instructions control the bus usage and execution
i. WAIT – Wait for Test input pin to go low.
ii. HLT – Halt the process.
iii. NOP – No operation.
iv. ESC – Escape to external device like NDP
v. LOCK – Bus lock instruction prefix.
Addressing Modes
Addressing modes of 8086
When 8086 executes an instruction, it performs the specified function on data. These data are called its operands and may be part of the instruction, reside in one of the internal registers of the microprocessor, stored at an address in memory or held at an I/O port, to access these different types of operands, the 8086 is provided with various addressing modes (Data Addressing Modes).
Data Addressing Modes of 8086
The 8086 has 12 addressing modes. The various 8086 addressing modes can be classified into five groups.
A. Addressing modes for accessing immediate and register data (register and immediate modes).
B. Addressing modes for accessing data in memory (memory modes)
C. Addressing modes for accessing I/O ports (I/O modes)
D. Relative addressing mode
E. Implied addressing mode
8086 ADDRESSING MODES
A. Immediate addressing mode:
In this mode, 8 or 16 bit data can be specified as part of the instruction.
Register addressing mode :
The operand to be accessed is specified as residing in an internal register of 8086. Fig.
below shows internal registers, any one can be used as a source or destination operand, however only the data registers can be accessed as either a byte or word.
B. Direct addressing mode :
The instruction Opcode is followed by an affective address, this effective address is directly used as the 16 bit offset of the storage location of the operand from the location specified by the current value in the selected segment register.
The default segment is always DS.
The 20 bit physical address of the operand in memory is normally obtained as
PA = DS : EA
But by using a segment override prefix (SOP) in the instruction, any of the four segment registers can be referenced,
The Execution Unit (EU) has direct access to all registers and data for register and immediate operands. However the EU cannot directly access the memory operands. It must use the BIU, in order to access memory operands.
In the direct addressing mode, the 16 bit effective address (EA) is taken directly from the displacement field of the instruction.
Example 1 : MOV CX, START
If the 16 bit value assigned to the offset START by the programmer using an assembler pseudo instruction such as DW is 0040 and [DS] = 3050. Then BIU generates the 20 bit physical address 30540 H.
The content of 30540 is moved to CL The content of 30541 is moved to CH
Example 2 : MOV CH, START
If [DS] = 3050 and START = 0040
8 bit content of memory location 30540 is moved to CH.
Example 3 : MOV START, BX
With [DS] = 3050, the value of START is 0040.
Physical address : 30540
MOV instruction moves (BL) and (BH) to locations 30540 and 30541 respectively.
Register indirect addressing mode :
The EA is specified in either pointer (BX) register or an index (SI or DI) register. The 20 bit physical address is computed using DS and EA.
String addressing mode:
The string instructions automatically assume SI to point to the first byte or word of the source operand and DI to point to the first byte or word of the destination operand. The contents of SI and DI are automatically incremented (by clearing DF to 0 by CLD instruction) to point to the next byte or word.
If [DX] = 5040
8 bit content by port 5040 is moved into AL.
Example 2 : IN AX, DX
Inputs 8 bit content of ports 5040 and 5041 into AL and AH respectively.
D. Relative addressing mode:
Example : JNC START
If CY=O, then PC is loaded with current PC contents plus 8 bit signed value of START, otherwise the next instruction is executed.
E. Implied addressing mode:
Instruction using this mode have no operands.
Example : CLC which clears carry flag to zero.
Special functions of general-purpose registers: AX & DX registers:
In 8 bit multiplication, one of the operands must be in AL. The other operand can be a byte in memory location or in another 8 bit register. The resulting 16 bit product is stored in AX, with AH storing the MS byte.
In 16 bit multiplication, one of the operands must be in AX. The other operand can be a word in memory location or in another 16 bit register. The resulting 32 bit product is stored in DX and AX, with DX storing the MS word and AX storing the LS word.
BX register : In instructions where we need to specify in a general purpose register the 16 bit effective address of a memory location, the register BX is used (register indirect).
CX register : In Loop Instructions, CX register will be always used as the implied counter.
In I/O instructions, the 8086 receives into or sends out data from AX or AL depending as a word or byte operation. In these instructions the port address, if greater than FFH has to be given as the contents of DX register.
Ex : IN AL, DX
DX register will have 16 bit address of the I/P device
Physical Address (PA) generation :
Generally Physical Address (20 Bit) = Segment Base Address (SBA)
Instruction Format :
The 8086 instruction sizes vary from one to six bytes. The OP code occupies six bytes and it defines the operation to be carried out by the instruction.
Register Direct bit (D) occupies one bit. It defines whether the register operand in byte 2 is the source or destination operand.
D=1 Specifies that the register operand is the destination operand.
D=0 indicates that the register is a source operand.
Data size bit (W) defines whether the operation to be performed is an 8 bit or 16 bit data
W=0 indicates 8 bit operation
W=1 indicates 16 bit operation
The second byte of the instruction usually identifies whether one of the operands is in memory or whether both are registers.
This byte contains 3 fields. These are the mode (MOD) field, the register (REG) field and the Register/Memory (R/M) field.
Register field occupies 3 bits. It defines the register for the first operand which is specified as source or destination by the D bit.
In the above, encoding of the R/M field depends on how the mode field is set. If MOD=11 (register to register mode), this R/M identifies the second register operand.
MOD selects memory mode, then R/M indicates how the effective address of the memory operand is to be calculated. Bytes 3 through 6 of an instruction are optional fields that normally contain the displacement value of a memory operand and / or the actual value of an immediate constant operand.
Example 1 : MOV CH, BL
This instruction transfers 8 bit content of BL
Into CH
The 6 bit Opcode for this instruction is 1000102 D bit indicates whether the register specified by the REG field of byte 2 is a source or destination operand.
D=0 indicates BL is a source operand.
W=0 byte operation
In byte 2, since the second operand is a register MOD field is 112.
The R/M field = 101 (CH)
Register (REG) field = 011 (BL)
Hence the machine code for MOV CH, BL is
10001000 11 011 101
Byte 1 Byte2
= 88DD16
Example 2 : SUB Bx, (DI)
This instruction subtracts the 16 bit content of memory location addressed by DI and DS from Bx. The 6 bit Opcode for SUB is 0010102.
D=1 so that REG field of byte 2 is the destination operand. W=1 indicates 16 bit operation.
MOD = 00
REG = 011
R/M = 101
Summary of all Addressing Modes
Example 3 : Code for MOV 1234 (BP), DX
Here we have specify DX using REG field, the D bit must be 0, indicating the DX is the source register. The REG field must be 010 to indicate DX register. The W bit must be 1 to indicate it is a word operation. 1234 [BP] is specified using MOD value of 10 and R/M value of 110 and a displacement of 1234H. The 4 byte code for this instruction would be 89 96 34 12H.
Example 4 : Code for MOV DS : 2345 [BP], DX
Here we have to specify DX using REG field. The D bit must be o, indicating that Dx is the source register. The REG field must be 010 to indicate DX register. The w bit must be 1 to indicate it is a word operation. 2345 [BP] is specified with MOD=10 and R/M = 110 and displacement = 2345 H.
Whenever BP is used to generate the Effective Address (EA), the default segment would be SS. In this example, we want the segment register to be DS, we have to provide the segment override prefix byte (SOP byte) to start with. The SOP byte is 001 SR 110, where SR value is provided as per table shown below.
Example 5 :
Give the instruction template and generate code for the instruction ADD OFABE [BX], [DI], DX (code for ADD instruction is 000000)
ADD OFABE [BX] [DI], DX
Here we have to specify DX using REG field. The bit D is 0, indicating that DX is the source register. The REG field must be 010 to indicate DX register. The w must be 1 to indicate it is a word operation. FABE (BX + DI) is specified using MOD value of 10 and R/M value of 001 (from the summary table). The 4 byte code for this instruction would be
Example 6 :
Give the instruction template and generate the code for the instruction MOV AX, [BX]
(Code for MOV instruction is 100010)
AX destination register with D=1 and code for AX is 000 [BX] is specified using 00 Mode and R/M value 111
It is a word operation
Questions :
1. Write a note on segment registers.
2. List the rules for segmentation.
3. What are the advantages of using segmentation?
4. What do you mean by index registers?
5. What is the function of SI and DI registers?
6. Explain the addressing modes of 8086 with the help of examples.
7. What do you mean by segment override prefix?
8. Write a short notes on i) Instruction formats ii) Instruction execution timing
9. Determine and explain the addressing modes of the following 8086 instructions.
i) PUSH BX ii) CALL BX iii) JMP DWORD PTR 6200 [BX]
iv) OR OABCD [BX] [SI], CX v) INT O
10. Give the instruction template and generate code for the instruction ADD OFABE [BX] [DI], DX (code for ADD instruction is 000 000)
11. Explain the special functions performed by general purpose registers of 8086.
12. Give the instruction template and generate the code for the instruction MOV AX, [BX].