Display Modes
There are various options of data display The first one is known as left entry mode or type writer mode. Since in a type writer the first character typed appears at the left-most position, while the subsequent characters appears successively to the right of the first one.
The other display format is known as right entry mode, or calculator mode, since the calculator the first character entered appears at the right-most position and this character is shifted one position left when the next character is entered.
1. Left Entry Mode
In the Left entry mode, the data is entered from the left side of the display unit. Address 0 of the display RAM contains the leftmost display character and address 15 of the RAM contains the rightmost display character.
2. Right Entry Mode
In the right entry mode, the first entry to be displayed is entered on the rightmost display. The next entry is also placed in the right most display but after the previous display is shifted left by one display position.
Command Words of 8279
All the Command words or status words are written or read with Ao = 1 and CS = 0 to or from 8279.
a. Keyboard Display mode set
The format of the command word to select different modes of operation of 8279 is given below with its bit definitions.
b. Programmable Clock
The clock for operation of 8279 is obtained by dividing the external clock input signal by a programmable constant called prescaler.
PPPPP is a 5-bit binary constant. The input frequency is divided by a decimal constant ranging from 2 to 31, decided by the bits of an internal prescalar, PPPPP.
c. Read FIFO/Sensor RAM
The format of this command is given as shown below
X – don’t care
AI – Auto increment flag
AAA – Address pointer to 8 bit FIFO RAM
This word is written to set up 8279 for reading FIFO/Sensor RAM. In scanned keyboard mode, AI and AAA bits are of no use. The 8279 will automatically drive data bus for each subsequent read, in the same sequence, in which the data was entered.
d. Read Display RAM
This command enables a programmer to read the display RAM data
The CPU writes this command word to 8279 to prepare it for display RAM read operation. AI is auto incremented flag and AAAA, the 4-bit address, points to the 16-byte display RAM that is to be read. If AI = 1, the address will be automatically, incremented after each read or write to the display RAM.
e. Write Display RAM
The format of this command is given as shown below
AI – Auto increment flag
AAAA – 4-bit address for 16-bit display RAM to be written Other details of this command are similar to the ‘Read Display RAM Command.
f. Display Write Inhibit/Blanking
The IW (Inhibit write flag) bits are used to mask the individual nibble Here Do and D2 corresponds to OUTBo – OUTB3 while D1 and D3 corresponds to OUTAo-OUTA3 for blanking and masking respectively.
g. Clear Display RAM
The CD2, CD1, CDo is a selectable blanking code to clear all the rows of the display RAM as given below. The characters A and B represents the output nibbles.
|
CD |
CD1 |
CDo |
|
|
1 |
0 |
x |
All Zeros (x don’t care) AB = 00 |
|
1 |
1 |
0 |
A3-Ao = 2(0010) and B3-Bo = 00(0000) |
|
1 |
1 |
1 |
All ones (AB = FF), i.e. clear RAM |
Here, CA represents clear All and CF represents Clear FIFO RAM
End Interrupt/Error Mode Set
For the sensor matrix mode, this command lowers the IRQ line and enables further writing into the RAM. Otherwise, if a charge in sensor value is detected, IRQ goes high that inhibits writing in the sensor RAM.
Key-code and status Data Formats
This briefly describes the formats of the Key-code/Sensor data in their respective modes of operation and the FIFO Status Word formats of 8279.
Key-code Data Formats :
After a valid Key closure, the key code is entered as a byte code into the FIFO RAM, in the following format, in scanned keyboard mode. The Keycode format contains 3-bit contents of the internal row counter, 3-bit contents of the column counter and status of the SHIFT and CNTL Keys The data format of the Keycode in scanned keyboard mode is given below.
In the sensor matrix mode, the data from the return lines is directly entered into an appropriate row of sensor RAM, that identifies the row of the sensor that changes its status. The SHIFT and CNTL Keys are ignored in this mode. RL bits represent the return lines.
Rn represents the sensor RAM row number that is equal to the row number of the sensor array in which the status change was detected. Data Format of the sensor code in sensor matrix mode
FIFO Status Word :
The FIFO status word is used in keyboard and strobed input mode to indicate the error. Overrun error occurs, when an already full FIFO is attempted an entry, Underrun error occurs when an empty FIFO read is attempted. FIFO status word also has a bit to show the unavailability of FIFO RAM because of the ongoing clearing operation.
In sensor matrix mode, a bit is reserved to show that at least one sensor closure indication is stored in the RAM, The S/E bit shows the simultaneous multiple closure error in special error mode. In sensor matrix mode, a bit is reserved to show that at least one sensor closure indication is stored in the RAM, The S/E bit shows the simultaneous multiple closure error in special error mode. The FIFO status word format is as shown below :
Interfacing and Programming 8279
Problem :
Interface keyboard and display controller 8279 with 8086 at address 0080H. Write an ALP to set up 8279 in scanned keyboard mode with encoded scan, N-Key rollover mode. Use a 16 character display in right entry display format. Then clear the display RAM with zeros. Read the FIFO for key closure. If any key is closed, store it’s code to register CL. Then write the byte 55 to all the displays, and return to DOS. The clock input to 8279 is 2MHz, operate it at 100KHz.
Solution :
Y The 8279 is interfaced with lower byte of the data bus, i.e. Do-D7 . Hence the Ao input of 8279 is connected with address lineA1.
Y The data register of 8279 is to be addressed as 0080H, i.e.Ao=0.
Y For addressing the command or status word Ao input of 8279 should be 1.
Y The next step is to write all the required command words for this problem.
Figure shows the interfacing schematic
Keyboard/Display Mode Set CW :
This command byte sets the 8279 in 16-character right entry and encoded scan N-Key rollover mode.
Program clock selection :
The clock input to 8279 is 2MHz, but the operating frequency is to be 100KHz, i.e. the clock input is to be divided by 20 (10100). Thus the prescalar value is 10100 and trhe command byte is set as given.
Clear Display RAM :
This command clears the display RAM with the programmable blanking code.
Read FIFO :
This command byte enables the programmer to read a key code from the FIFO RAM
Write Display RAM :
This command enables the programmer to write the addressed display locations of the RAM as presented below.
Programmable timer device 8253
Intel’s programmable counter/timer device (8253) facililitates the
generation of accurate time delays. When 8253 is used as timing and delay generation peripheral, the microprocessor becomes free from the
tasks related to the counting process and execute the programs in
memory, while the timer device may perform the counting tasks. This minimizes the software overhead on the microprocessor.
Architecture and Signal Descriptions
The programmable timer device 8253 contains three independent 16-bit counters, each with a maximum count rate of 2.6 MHz. It is thus possible to generate three totally independent delays or maintain three independent counters simultaneously. All the three counters may be independently controlled by programming the three internal command word registers.
The 8-bit, bidirectional data buffer interfaces internal circuit of 8253 to microprocessor systems bus. Data is transmitted or received by the buffer upon the execution of IN or OUT instruction. The read/write logic controls the direction of the data buffer depending upon whether it is a read or a write operation. It may be noted that IN instruction reads data while OUT instruction writes data to a peripheral. The internal block diagram and pin diagram of 8253 are shown in Fig. 1 and l.1 respectively.
Fig1.1 Pin Configuration of 8253
The three counters available in 8253 are independent of each other in operation, but they are identical to each other in organization. These are all 16-bit presettable, down counters, able to operate either in BCD or in hexadecimal mode. The mode control word register contains the information that can be used for writing or reading the count value into or from the respective count register using the OUT and IN instructions. The specialty of the 8253 counters is that they can be easily read on line without disturbing the clock input to the counter. This facility is called as "on the fly" reading of counters, and is invoked using a mode control word.
A0, Al pins are the address input pins and are required internally for addressing the mode control word registers and the three counter registers. A low on CS line enables the 8253. No operation will be performed by 8253 till it is enabled. Table 1 shows the selected operations for various control inputs.
A control word register accepts the 8-bit control word written by the microprocessor and stores it for controlling the complete operation of the specific counter. It may be noted that, the control word register can only be written and cannot be read as it is obvious from Table 1. The CLK, GATE and OUT pins are available for each of the three timer channels. Their functions will be clear when we study the different operating modes of 8253.
Control Word Register
The 8253 can operate in anyone of the six different modes. A control word must be written in the respective control word register by the microprocessor to initialize each of the counters of 8253 to decide its operating mode. Each of the counters works independently depending upon the control word decided by the programmer as per the needs. In other words, all the counters can operate in anyone of the modes or they may be even in different modes of operation, at a time. The control word format is presented, along with the definition of each bit, in Fig. 1.2
While writing a count in the counter, it should be noted that, the count is written in the counter only after the data is put on the data bus and a falling edge appears at the clock pin of the peripheral thereafter. Any reading operation of the counter, before the falling edge appears may result in garbage data.
With this much information, on the general functioning of 8253, one may proceed further for the details of the operating modes of 8253.
However, the concepts shall be clearer after one goes through the interfacing examples and the related assembly language programs.
