MINIMUM MODE VERSUS MAXIMUM MODE
There are two available modes of operation for the 8086/8088 microprocessors: minimum mode and maximum mode. Minimum mode operation is obtained by connecting the mode selection pin MN>MX to +5.0 V, and maximum mode is selected by grounding this pin. Both modes enable different control structures for the 8086/8088 microprocessors. The mode of operation provided by minimum mode is similar to that of the 8085A, the most recent Intel 8-bit micro- processor. The maximum mode is unique and designed to be used whenever a coprocessor exists in a system. Note that the maximum mode was dropped from the Intel family beginning with the 80286 microprocessor.
Minimum Mode Operation
Minimum mode operation is the least expensive way to operate the 8086/8088 microprocessors (see Figure 9–19 for the minimum mode 8088 system). It costs less because all the control sig- nals for the memory and I/O are generated by the microprocessor. These control signals are identical to those of the Intel 8085A, an earlier 8-bit microprocessor. The minimum mode allows the 8085A 8-bit peripherals to be used with the 8086/8088 without any special considerations.
Maximum Mode Operation
Maximum mode operation differs from minimum mode in that some of the control signals must be externally generated. This requires the addition of an external bus controller—the 8288 bus controller (see Figure 9–20 for the maximum mode 8088 system). There are not enough pins on the 8086/8088 for bus control during maximum mode because new pins and new features have replaced some of them. Maximum mode is used only when the system contains external coprocessors such as the 8087 arithmetic coprocessor.
The 8288 Bus Controller
An 8086/8088 system that is operated in maximum mode must have an 8288 bus controller to provide the signals eliminated from the 8086/8088 by the maximum mode operation. Figure 9–21 illustrates the block diagram and pin-out of the 8288 bus controller.
Notice that the control bus developed by the 8288 bus controller contains separate signals for I/O (IORC and IOWC) and memory (MRDC and MWTC). It also contains advanced memory (AMWC) and I/O (AIOWC) write strobes, and the INTA signal. These signals replace the minimum mode ALE, WR, IO/M, DT/R, DEN, and INTA, which are lost when the 8086/8088 microprocessors are operated in the maximum mode.
Pin Functions
The following list provides a description of each pin of the 8288 bus controller.
S2, S1, and S0 Status inputs are connected to the status output pins on the 8086/8088 microprocessor. These three signals are decoded to generate the timing signals for the system.
CLK The clock input provides internal timing and must be connected to the CLK output pin of the 8284A clock generator.
ALE The address latch enable output is used to demultiplex the address/data bus.
DEN The data bus enable pin controls the bidirectional data bus buffers in the system. Note that this is an active high output pin that is the opposite polarity from the DEN signal found on the microprocessor when operated in the minimum mode.
DT>R AEN
The data transmit/receive signal is output by the 8288 to control the direction of the bidirectional data bus buffers.
The address enable input causes the 8288 to enable the memory control signals.
CEN The control enable input enables the command output pins on the 8288.
IOB The I/O bus mode input selects either the I/O bus mode or system bus mode operation.
AIOWC
IORC IOWC AMWT
MWTC MRDC
INTA
MCE>PDEN
The advanced I/O write is a command output used to provide I/O with an advanced I/O write control signal.
The I/O read command output provides I/O with its read control signal. The I/O write command output provides I/O with its main write signal. The advanced memory write control pin provides memory with an early or advanced write signal.
The memory write control pin provides memory with its normal write control signal.
The memory read control pin provides memory with a read control signal. The interrupt acknowledge output acknowledges an interrupt request input applied to the INTR pin.
The master cascade/peripheral data output selects cascade operation for an interrupt controller if IOB is grounded, and enables the I/O bus transceivers if IOB is tied high.