ADDRESS DECODING
In order to attach a memory device to the microprocessor, it is necessary to decode the address sent from the microprocessor. Decoding makes the memory function at a unique section or partition of the memory map. Without an address decoder, only one memory device can be connected to a microprocessor, which would make it virtually useless. In this section, we describe a few of the more common address-decoding techniques, as well as the decoders that are found in many systems.
Why Decode Memory?
When the 8088 microprocessor is compared to the 2716 EPROM, a difference in the number of address connections is apparent—the EPROM has 11 address connections and the microprocessor has 20. This means that the microprocessor sends out a 20-bit memory address whenever it reads or writes data. Because the EPROM has only 11 address pins, there is a mismatch that must be corrected. If only 11 of the 8088’s address pins are connected to the memory, the 8088 will see only 2K bytes of memory instead of the 1M bytes that it “expects” the memory to contain. The decoder corrects the mismatch by decoding the address pins that do not connect to the memory component.
Simple NAND Gate Decoder
When the 2K × 8 EPROM is used, address connections A10–A0 of the 8088 are connected to address inputs A10–A0 of the EPROM. The remaining nine address pins (A19–A11) are connected to the inputs of a NAND gate decoder (see Figure 10–13). The decoder selects the EPROM from one of the 2K-byte sections of the 1M-byte memory system in the 8088 microprocessor.
In this circuit, a single NAND gate decodes the memory address. The output of the NAND gate is a logic 0 whenever the 8088 address pins attached to its inputs (A19–A11) are all logic 1s. The active low, logic 0 output of the NAND gate decoder is connected to the CE input pin that selects (enables) the EPROM. Recall that whenever CE is a logic 0, data will be read from the EPROM only if OE is also a logic 0. The OE pin is activated by the 8088 RD signal or the MRDC (memory read control) signal of other family members.
If the 20-bit binary address, decoded by the NAND gate, is written so that the leftmost nine bits are 1s and the rightmost 11 bits are don’t cares (X), the actual address range of the EPROM can be determined. (A don’t care is a logic 1 or a logic 0, whichever is appropriate.)
Example 10–1 illustrates how the address range for this EPROM is determined by writing down the externally decoded address bits (A19–A11) and the address bits decoded by the EPROM (A10–A0) as don’t cares. We really do not care about the address pins on the EPROM because they are internally decoded. As the example illustrates, the don’t cares are first written as 0s to locate the lowest address and then as 1s to find the highest address. Example 10–1 also shows these binary boundaries as hexadecimal addresses. Here, the 2K EPROM is decoded at memory address locations FF800H–FFFFFH. Notice that this is a 2K-byte section of the memory and is also located at the reset location for the 8086/8088 (FFFF0H), the most likely place for an EPROM in a system.
Although this example serves to illustrate decoding, NAND gates are rarely used to decode memory because each memory device requires its own NAND gate decoder. Because of the excessive cost of the NAND gate decoder and inverters that are often required, this option requires that an alternate be found.
The 3-to-8 Line Decoder (74LS138)
One of the more common, although not only, integrated circuit decoders found in many microprocessor-based systems is the 74LS138 3-to-8 line decoder. Figure 10–14 illustrates this decoder and its truth table.
The truth table shows that only one of the eight outputs ever goes low at any time. For any of the decoder’s outputs to go low, the three enable inputs (G2A, G2B, and G1) must all be active. To be active, the G2A and G2B inputs must both be low (logic 0), and G1 must be high (logic 1). Once the 74LS138 is enabled, the address inputs (C, B, and A) select which output pin
goes low. Imagine eight EPROM CE inputs connected to the eight outputs of the decoder! This is a very powerful device because it selects eight different memory devices at the same time. Even today this device still finds wide application.
Sample Decoder Circuit. Notice that the outputs of the decoder, illustrated in Figure 10–15, are connected to eight different 2764 EPROM memory devices. Here, the decoder selects eight 8K- byte blocks of memory for a total memory capacity of 64K bytes. This figure also illustrates the address range of each memory device and the common connections to the memory devices. Notice that all of the address connections from the 8088 are connected to this circuit. Also, notice that the decoder’s outputs are connected to the CE inputs of the EPROMs, and the RD signal from the 8088 is connected to the OE inputs of the EPROMs. This allows only the selected EPROM to be enabled and to send its data to the microprocessor through the data bus whenever RD becomes a logic 0.
In this circuit, a three-input NAND gate is connected to address bits A19–A17. When all three address inputs are high, the output of this NAND gate goes low and enables input G2B of the 74LS138. Input G1 is connected directly to A16. In other words, in order to enable this decoder, the first four address connections (A19–A16) must all be high.
The address inputs C, B, and A connect to microprocessor address pins A15–A13. These three address inputs determine which output pin goes low and which EPROM is selected when- ever the 8088 outputs a memory address within this range to the memory system.
Example 10–2 shows how the address range of the entire decoder is determined. Notice that the range is location F0000H–FFFFFH. This is a 64K-byte span of the memory.
How is it possible to determine the address range of each memory device attached to the decoder’s outputs? Again, the binary bit pattern is written down; this time the C, B, and A address inputs are not don’t cares. Example 10–3 shows how output 0 of the decoder is made to go low to select the EPROM attached to that pin. Here, C, B, and A are shown as logic 0s.
If the address range of the EPROM connected to output 1 of the decoder is required, it is determined in exactly the same way as that of output 0. The only difference is that now the C, B, and A inputs contain a 001 instead of a 000 (see Example 10–4). The remaining output address ranges are determined in the same manner by substituting the binary address of the output pin into C, B, and A.
The Dual 2-to-4 Line Decoder (74LS139)
Another decoder that finds some application is the 74LS139 dua1 2-to-4 line decoder. Figure 10–16 illustrates both the pin-out and the truth table for this decoder. The 74LS139 contains two separate 2-to-4 line decoders—each with its own address, enable, and output connections.
A more complicated decoder using the 74LS139 decoder appears in Figure 10–17. This circuit uses a 128K × 8 EPROM (271000) and a 128K × 8 SRAM (621000). The EPROM is decoded at memory locations E0000H–FFFFFH and the SRAM is decoded at addresses 00000H–1FFFFH. This is fairly typical of a small embedded system, where the EPROM is located at the top of the memory space and the SRAM at the bottom.
Output Y0 of decoder U1A activates the SRAM whenever address bits A17 and A18 are both logic 0s if the IO>M signal is a logic 0 and address line A19 is a logic 0. This selects the SRAM for any address between 00000H and 1FFFFH. The second decoder (U1B) is slightly more complicated because the NAND gate (U4B) selects the decoder when IO>M is a logic 0 while A19 is a logic 1. This selects the EPROM for addresses E0000H through FFFFFH.
PLD Programmable Decoders
This section of the text explains the use of the programmable logic device, or PLD, as a decoder. There are three SPLD (simple PLD) devices that function in the same manner but have different names: PLA (programmable logic array), PAL (programmable array logic), and GAL (gated array logic). Although these devices have been in existence since the mid-1970s, they have only appeared in memory system and digital designs since the early 1990s. The PAL and the PLA are fuse-programmed, as is the PROM, and some PLD devices are erasable devices (as are EPROMs). In essence, all three devices are arrays of logic elements that are programmable.
Other PLDs are also available, such as CPLDs (complex programmable logic devices), FPGAs (field programmable gate arrays), and FPICs (field programmable interconnect). These types of PLDs are much more complex than the SPLDs that are used more commonly in designing a complete system. If the concentration is on decoding addresses, the SPLD is used and if the concentration is on a complete system, then the CPLD, FPLG, or FPIC is used to implement the design. These devices are also referred to as an ASIC (application-specific integrated circuit).
Combinatorial Programmable Logic Arrays. One of the two basic types of PALs is the combinatorial programmable logic array. This device is internally structured as a programmable array of combinational logic circuits. Figure 10–18 illustrates the internal structure of the PAL16L8 that is constructed with AND/OR gate logic. This device, which is representative of a PLD, has 10 fixed inputs, two fixed outputs, and six pins that are programmable as inputs of outputs. Each output sig- nal is generated from a seven-input OR gate that has an AND gate attached to each input. The out- puts of the OR gates pass through a three-state inverter that defines each output as an AND/NOR function. Initially, all of the fuses connect all of the vertical/horizontal connections illustrated in Figure 10–18. Programming is accomplished by blowing fuses to connect various inputs to the OR gate array. The wired-AND function is performed at each input connection, which allows a product term of up to 16 inputs. A logic expression using the PAL16L8 can have up to seven product terms with up to 16 inputs NORed together to generate the output expression. This device is ideal as a memory address decoder because of its structure. It is also ideal because the outputs are active low.
Fortunately, we don’t have to choose the fuses by number for programming, as was customary when this device was first introduced. A PAL is programmed with a software package such as PALASM, the PAL assembler program. More recently, PLD design is accomplished using HDL (hardware description language) or VHDL (verilog HDL). The VHDL language and its syntax are currently the industry standard for programming PLD devices. Example 10–5 shows a pro- gram that decodes the same areas of memory as decoded in Figure 10–17. Note that this program
was developed by using a text editor such as EDIT, available with Microsoft DOS version 7.1 with XP or NotePad in Windows. The program can also be developed by using an editor than comes with any of the many programming packages for PLDs. Various editors attempt to ease the task of defining the pins, but we believe it is easier to use NotePad and the listing as shown.
Comments in VHDL programming begin with a pair of minus signs as illustrated in the first line of the VHDL code in Example 10–5. The library and use statements specify the standard IEEE library using standard logic. The entity statement names the VHDL module, in this case DECODER_10_17. The port statements define the in, out, and in-out pins used in the equations for the logic expression, which appears in the begin block. A19, A18, A17, and MIO (this signal cannot be defined as IO>M so it was called MIO) are defined as input pins and ROM and RAM are the output pins for connection to the CS pins on the memory devices. The architecture statement merely refers to the version (V1) of this design. Finally, the equations for the design are placed in the begin block. Each output pin has its own equation. The key- word not is used for logical inversion and the keyword and is used for the logical and opera- tion. In this case the ROM equation causes the ROM pin to become a logic zero only when the A19, A18, A17, and MIO are all logic zeros (00000H–1FFFFH). The RAM equation causes the RAM pin to become a logic zero when A18 and A17 are all ones at the same time that MIO is a logic zero. A19 is connected to the active high CE2 pin after being inverted by the PLD. The RAM is selected for addresses 60000H–7FFFFH. See Figure 10–19 for the PLD realization of Example 10–5.
