PENTIUM THROUGH CORE2 (64-BIT) MEMORY INTERFACE
The Pentium through Core2 microprocessors (except for the P24T version of the Pentium) contain a 64-bit data bus, which requires either eight decoders (one per bank) or eight separate write signals. In most systems, separate write signals are used with this microprocessor when interfacing memory. Figure 10–36 illustrates the Pentium’s memory organization and its eight memory banks. Notice that this is almost identical to the 80486, except that it contains eight banks instead of four.
As with earlier versions of the Intel microprocessor, this organization is required for upward memory compatibility. The separate write strobe signals are obtained by combining the bank enable signals with the MWTC signal, which is generated by combining the M>IO with W>R. The circuit employed for bank write signals appears in Figure 10–37. As can be imagined, we often find a PLD used for bank write signal generation.
64-Bit Memory Interface
Figure 10–38 illustrates a small Pentium–Core2 memory system. This system uses a PLD to decode the memory address. This system contains eight 27C4001 EPROM memory devices (512K × 8), interfaced to the Pentium–Core2 at locations FFC00000H through FFFFFFFFH.
This is a total memory size of 4M bytes organized so that each bank contains two memory components. Note that the Pentium Pro through the Core2 can be configured with 36 address connections, allowing up to 64G of memory. The Pentium 4 and the Core2 can also be configured in the flat mode and may contain up to 40 address connections. (The Core2 contains only 36.)
Memory decoding, as illustrated in Example 10–10, is similar to the earlier examples, except that with the Pentium–Core2 the rightmost three address bits (A2–A0) are ignored. In this case, the decoder selects sections of memory that are 64 bits wide and contain 4M bytes of EPROM memory.
The A0 address input of each memory device connects to the A3 address output of the Pentium and above. This A1 address input of each memory device connects to the A4 address output of the Pentium and above. This skewed address connection continues until the A18 address input to the memory is connected to the A22 address output of the Pentium. Address positions A22–A31 are decoded by PLD. The program for the PLD device is listed in Example 10–10 for memory locations FFC00000H–FFFFFFFFH.
Not explained in this text is the memory interface for an Itanium and Itanium II from Intel, which contains a data bus width of 128 bits. From the information presented in this section of the chapter, it is a fairly easy task to create a memory with 16 banks for the Itanium.