DYNAMIC RAM
Because RAM memory is often very large, it requires many SRAM devices at a great cost or just a few DRAMs (dynamic RAMs) at a much reduced cost. The DRAM memory, as briefly dis- cussed in Section 10–1, is fairly complex because it requires address multiplexing and refreshing. Luckily, the integrated circuit manufacturers have provided a dynamic RAM controller that includes the address multiplexers and all the timing circuitry necessary for refreshing.
This section of the text covers the DRAM memory device in much more detail than in Section 10–1 and provides information on the use of a dynamic controller in a memory system.
DRAM Revisited
As mentioned in Section 10–1, a DRAM retains data for only 2–4 ms and requires the multiplexing of address inputs. Although address multiplexers have already been covered in Section 10–1, the operation of the DRAM during refresh is explained in detail here.
As previously mentioned, a DRAM must be refreshed periodically because it stores data internally on capacitors that lose their charge in a short period of time. To refresh a DRAM, the contents of a section of the memory must periodically be read or written. Any read or write automatically refreshes an entire section of the DRAM. The number of bits that are refreshed depends on the size of the memory component and its internal organization.
Refresh cycles are accomplished by doing a read, a write, or a special refresh cycle that doesn’t read or write data. The refresh cycle is internal to the DRAM and is often accomplished while other memory components in the system operate. This type of memory refresh is called either hidden refresh, transparent refresh, or sometimes cycle stealing.
In order to accomplish a hidden refresh while other memory components are functioning, an RAS-only cycle strobes a row address into the DRAM to select a row of bits to be refreshed. The RAS input also causes the selected row to be read out internally and rewritten into the selected bits. This recharges the internal capacitors that store the data. This type of refresh is
hidden from the system because it occurs while the microprocessor is reading or writing to other sections of the memory.
The DRAM’s internal organization contains a series of rows and columns. A 256K × 1 DRAM has 256 columns, each containing 256 bits, or rows organized into four sections of 64K bits each. Whenever a memory location is addressed, the column address selects a column (or internal memory word) of 1024 bits (one per section of the DRAM). Refer to Figure 10–39 for the internal structure of a 256K × 1 DRAM. Note that larger memory devices are structured similarly to the 256K × 1 device. The difference usually lies in either the size of each section or the number of sections in parallel.
Figure 10–40 illustrates the timing for an RAS-only refresh cycle. The difference between the RAS and a read or write is that it applies only a refresh address, which is usually obtained from a 7- or 8-bit binary counter. The size of the counter is determined by the type of DRAM being refreshed. The refresh counter is incremented at the end of each refresh cycle so all the rows are refreshed in 2 or 4 ms, depending on the type of DRAM.
If there are 256 rows to be refreshed within 4 ms, as in a 256K × 1 DRAM, then the refresh cycle must be activated at least once every 15.6 μs in order to meet the refresh specification. For example, it takes the 8086/8088, running at a 5 MHz clock rate, 800 ns to do a read or a write. Because the DRAM must have a refresh cycle every 15.6 μs, for every 19 memory reads or writes, the memory system must run a refresh cycle or else memory data will be lost. This represents a loss of 5% of the computer’s time, a small price to pay for the savings represented by using the dynamic RAM. In a modern system such as a 3.0 GHz Pentium 4, 15.6 μs is a great deal of time. Since the 3.0 GHz Pentium 4 executes an instruction in about one-third ns (many instructions exe- cute in a single clock), it can execute about 46,000 instructions between refreshes. This means that in the new machines much less than 1% (≈ 0.002 %) is required for a refresh.
EDO Memory
A slight modification to the structure of the DRAM changes the device into an EDO (extended data output) DRAM device. In the EDO memory, any memory access, including a refresh, stores the 256 bits selected by RAS into latches. These latches hold the next 256 bits of informa- tion, so in most programs, which are sequentially executed, the data are available without any wait states. This slight modification to the internal structure of the DRAM increases system per- formance by about 15% to 25%. Although EDO memory is no longer available, this technique is still employed in all modern DRAM.
SDRAM
Synchronous dynamic RAM (SDRAM) is used with most newer systems in one form or another because of its speed. Versions are available with access times of 10 ns for use with a 66 MHz sys- tem bus; 8 ns for use with a 100 MHz system bus; and 7 ns for the 133 MHz bus. At first, the access time may lead one to think that these devices operate without wait states, but that is not true. After all, DRAM access time is 60 ns and SDRAM access time is 10 ns. The 10 ns access time is misleading because it only applies to the second, third, and fourth 64-bit reads from the device. The first read requires the same number of waits as a standard DRAM.
When a burst transfer occurs to the SDRAM from the microprocessor, it takes three or four bus clocks before the first 64-bit number is read. Each subsequent number is read without wait states and in one bus cycle each. Because SDRAM bursts read four 64-bit numbers, and the second through the fourth require no waits and can be read in one bus cycle each, SDRAM outperforms standard DRAM or even EDO memory. This means that if it takes three bus cycles for the first number and three more for the next three, it takes a total of seven bus clocks to read four 64-bit numbers. If this is compared to DRAM, which takes three clocks per number or 12 clocks,
you can see the increase in speed. Most estimates place SDRAM at about a 10% performance increase over EDO memory.
DDR
Double-data rate (DDR) memory is the latest improvement in a long string of modifications to DRAM. The DDR memory transfers data at double the rate of an SDRAM because it transfers data on each edge of the clock. The positive edge is used for a transfer and so is the negative edge. Even though this seems as if it doubles the speed of the memory, it really does not. The main rea- son is that the access time problem still exists, with even the most advanced memory requiring an access time of 40 ns. If you think about a microprocessor running at many GHz, this is a very long time to wait for the memory. Hence, the speed will not always be double as the name might suggest.
DRAM Controllers
In most systems, a DRAM controller-integrated circuit performs the task of address multiplexing and the generation of the DRAM control signals. Some newer embedded microprocessors, such as the 80186/80188, include the refresh circuitry as a part of the microprocessor. Most modern computers contain the DRAM controller in the chip set so a stand-alone DRAM controller is not available. The DRAM controller in the chip set for the microprocessor times refresh cycles and inserts refresh cycles into the timing. The memory refresh is transparent to the microprocessor, because it really does not control refreshing.
For the Pentium II, III, and Pentium 4, the DRAM controller is built into the chip set provided by Intel or AMD. It has been many years since a separate DRAM controller has been used to build a computer system. In the future, even the chip set will undoubtedly be built into the microprocessor.