SPECIAL PENTIUM REGISTERS
The Pentium is essentially the same microprocessor as the 80386 and 80486, except that some additional features and changes to the control register set have occurred. This section highlights the differences between the 80386 control register structure and the flag register.
Control Registers
Figure 18–8 shows the control register structure for the Pentium microprocessor. Note that a new control register, CR4, has been added to the control register array.
This section of the text only explains the new Pentium components in the control registers.
See Figure 17-14 for a description and illustration of the 80386 control registers. Following is a description of the new control bits and new control register CR4:
CD Cache disable controls the internal cache. If CD = 1, the cache will not fill with new data for cache misses, but it will continue to function for cache hits. If CD = 0, misses will cause the cache to fill with new data.
NW Not write-through selects the mode of operation for the data cache. If NW = 1, the data cache is inhibited from cache write-through.
AM Alignment mask enables alignment checking when set. Note that alignment checking only occurs for protected mode operation when the user is at privilege level 3.
WP Write protect protects user-level pages against supervisor-level write operations.
When WP = 1, the supervisor can write to user-level segments.
NE Numeric error enables standard numeric coprocessor error detection. If NE = 1, the FERR pin becomes active for a numeric coprocessor error. If NE = 0, any coprocessor error is ignored.
VME Virtual mode extension enables support for the virtual interrupt flag in protected mode. If VME = 0, virtual interrupt support is disabled.
PVI Protected mode virtual interrupt enables support for the virtual interrupt flag in protected mode.
TSD Time stamp disable controls the RDTSC instruction.
DE Debugging extension enables I/O breakpoint debugging extensions when set.
PSE Page size extension enables 4M-byte memory pages when set.
MCE Machine check enable enables the machine checking interrupt.
The Pentium contains new features that are controlled by CR4 and a few bits in CR0. These new features are explained in later sections of the text.
EFLAG Register
The extended flag (EFLAG) register has been changed in the Pentium microprocessor. Figure 18–9 pictures the contents of the EFLAG register. Note that four new flag bits have been added to this register to control or indicate conditions about some of the new features in the Pentium. Following is a list of the four new flags and the function of each:
ID The identification flag is used to test for the CPUID instruction. If a program can set and clear the ID flag, the processor supports the CPUID instruction.
VIP Virtual interrupt pending indicates that a virtual interrupt is pending.
VIF Virtual interrupt is the image of the interrupt flag IF used with VIP.
AC Alignment check indicates the state of the AM bit in control register 0.
Built-In Self-Test (BIST)
The built-in self-test (BIST) is accessed on power-up by placing a logic 1 on INIT while the RESET pin changes from 1 to 0. The BIST tests 70% of the internal structure of the Pentium in approximately 150 μs. Upon completion of the BIST, the Pentium reports the outcome in regis- ter EAX. If EAX = 0, the BIST has passed and the Pentium is ready for operation. If EAX con- tains any other value, the Pentium has malfunctioned and is faulty.