OFF-CHIP DATA MEMORY
Context
● You are developing an embedded application using one or more members of the 8051 family of microcontrollers.
● You are designing an appropriate hardware foundation for your application.
Problem
How do you add up to 64 kbytes of external RAM to your Standard 8051 microcontroller?
Background
To add external data memory to an 8051 we first need to understand the memory interface. An overview of this interface is shown in Figure 6.2 and will be referred to in the discussions that follow.
The address bus (P0.0–P0.7)
For both program and data access, Port 0 is used as a multiplexed address/data bus that outputs the low-order address bits (A0–A7) and inputs/outputs the 8-bit data (D0–D7).
The data bus (P2.0–P2.7)
For all external program accesses, P2 outputs the high-order address bits (A8–A15). The same is true for external data accesses with 16-bit addresses.
Note one special case: Systems that use on-chip code memory and only 256 bytes of external data memory are free to use P2 for general purpose I/O.
ALE (address latch enable)
ALE is used to demultiplex the AD0–7 bus. At the beginning of the external cycle ALE is high and the CPU emits A0–A7 which should be externally latched when ALE goes low.
Note that on most 8051-based systems, ALE is always active, even during internal program and data accesses: however, on some more modern 8051 designs, it is possi- ble to disable ALE activity if external memory access is not required: this can help to reduce EM emissions.
Note also that, where external memory access is not required, ALE may be treated as a continuous clock that runs at one-sixth the oscillator frequency. This output can be used, for example, to control timing in external circuits.
PSEN (program store enable)
PSEN is the read strobe for external instruction (code memory) access. Unlike ALE, PSEN is not asserted during internal accesses. We consider the use of PSEN in the pattern OFF – CHIP CODE MEMOR Y [page 100].
RD (data read)
RD is the read strobe for external data access and (like PSEN) is not asserted during internal accesses.
WR (data write)
WR is the write strobe for external data access and (like PSEN and RD) is not asserted during internal accesses.
Solution
With a basic understanding of the memory interface (see ‘Background’), adding exter- nal data memory to an 8051 microcontroller is easy to do, provided some care is taken in the choice of components (see Figure 6.3).
[Note that, if the microcontroller is not a CMOS device and the memory devices are CMOS devices, you will require pull-up resistors (not shown) on Port 0. This is most easily achieved using a DIL (or similar) 10K resistor pack.]
Note that the 74×373 and the 74×375 are functionally identical, but have different pin arrangements. The ’375 arrangement is usually easier to wire up. Both latches are available in different speed ratings: inevitably, the cost increases with the speed.
Recommended latch and (RAM) memory combinations for a wide range of clock speeds are given in Table 6.2. These are taken from Dallas Application Note 89: how- ever, latch and memory combinations which will operate with these Dallas devices will also work with most other (generally slower) 8051 devices.
Hardware resource implications
Use of external memory has major resource implications: it requires the use of two ports (P0 and P2), plus two pins (P3.6, P3.7) on Port 3. This reduces the number of available port pins from 32 to 14. See the following for additional comments on this.
Reliability and safety implications
As discussed in ON – CHIP MEMOR Y [page 82], the addition of external memory can reduce the reliability of you application: use an on-chip solution where possible.
However, as many 8051s simply do not have enough RAM to support larger appli- cations and you will be forced to use off-chip RAM in some applications. When you
TABLE 6.2 Recommended latch and (RAM) memory combinations for a wide range of clock speeds (adapted from Dallas Application Note 89)
do use off-chip memory (code or data), please note that one of the most common errors made by inexperienced 8051 developers is to continue to use P0, P2 or P3 as normal I/O ports when using external memory. This cannot be done (for reasons discussed in ‘Hardware resource implications’).
In short: if you use external memory, you cannot safely use P0 and P2 for any other purpose, and you must also take care when writing to Port 3.
For example, any statement similar to this:
P3 = AD_data;
is potentially catastrophic.
Instead, make use of sbit variables to ensure you only write to ‘safe’ port pins: see
PORT I / O [page 174] for further details.
Portability
Hardware designs for external memory are generally portable. However, if you upgrade from a ‘slow’ to a ‘fast’ processor (or simply increase the crystal frequency) you need to make sure that the external latch and memory components are suffi- ciently fast: refer to Table 6.2 for suggestions.
The only way to make your external access design as portable as possible is always to use the fastest external components available. This approach has cost implications, but, if you are able to produce 100,000 copies of one, generic (fast) board rather than smaller numbers of ‘slow’, ‘medium’ and ‘fast’ versions, you may find the ‘one size fits all’ solution to be both a reliable and cost-effective solution.
Overall strengths and weaknesses
Many 8051s simply do not have enough RAM to support larger applications: this pattern solves that problem.
As discussed in ON –CHIP MEMORY [page 82], the addition of external memory can reduce the reliability of your application: use an on-chip solution where possible.
Related patterns and alternative solutions
See ON – CHIP MEMOR Y [page 82] for a discussion on the use of on-chip memory.
Example: Using external RAM and internal XRAM on the C509
The Infineon C509 microcontrollers have 3 kbytes of internal XRAM. By default, XRAM is disabled when the device is reset and the full 64 kbytes of external data memory are accessible.
However, if XRAM is enabled, then the internal XRAM and external RAM memory areas overlap: specifically, in the case of the C509, the XRAM is mapped to the upper 3 kbytes of data memory, as illustrated in Figure 6.4.
The internal XRAM is enabled via the SYSCON1 SFR. Specifically, the PRGEN bit must be set to 0 and the SWAP bit must be set to 1.
Example: Using external RAM and internal SRAM on the Dallas 8XC520
The Dallas 8XC520 microcontrollers have 1 kbyte of internal ‘SRAM’. By default, this SRAM is disabled when the device is reset and the full 64 kbytes of external data memory are accessible. However, if SRAM is enabled, then the internal XRAM and external RAM memory areas overlap: specifically, in the case of the 8XC520, the SRAM is mapped to the lowest 1 kbyte of data memory, as illustrated in Figure 6.5.
