Execution Cycle
Program execution is illustrated in Figure 1.7. Assuming that the application program code is in RAM, the program execution cycle proceeds as follows:
1. The CPU outputs (1) the address of the memory location containing the required instruction (this address is kept in the program counter). The sample address is shown in hexadecimal form (3A24) in Figure 1.7, but it is output in binary form on the address lines from the processor (for an explanation of hex numbering see Appendix A). The address decoder logic uses the address to select the RAM chip that has been allocated to this address. The address bus also connects directly to the RAM chip to select the individual location, giving a two-stage memory location select process.
2. The instruction code is returned to the CPU from the RAM chip via the data bus (2). The CPU reads the instruction from the data bus into an instruction register. The CPU then decodes and executes the instruction (3). The operands (code to be processed) are fetched
(4) from the following locations in RAM via the data bus, in the same way as the instruction.
3. The instruction execution continues by feeding the operand(s) to the data processing logic (5). Additional data can be fetched from memory (6). The result of the operation is stored in a data register (7), and then, if necessary, in memory (8) for later use. In the meantime, the program counter has been incremented (increased) to the address of the next instruction code. The address of the next instruction is then output and the sequence repeats from step 2.
The operating system, the application program and the user data are stored in different parts of RAM during program execution, and the application program calls up operating system
routines as required to read in, process and store the data. PC processors have multi-byte instructions, which are stored in multiple 8-bit locations, and use complex memory management techniques to speed up program execution.