Block Diagram
A somewhat simplified internal architecture (Figure 5.1) has been derived from the block diagram given in the data sheet. Some features seen in the manufacturer’s diagram have been left out because they are not important at this stage. The functional blocks of the chip are shown, with the main address paths identified. The bit width of each parallel path is indicated, with the 8-bit data bus connected to all the main registers. The timing and control block has control connections to all other blocks, which determine the processor operation at any point in time, but they are not all shown explicitly in order to keep the diagram as clear as possible.
The file register set contains various control and status registers, as well as the port registers and the program counter. The most commonly used are the ports (PORTA, PORTB), status register (STATUS), real-time clock counter (TMR0) and interrupt control (INTCON). There is also a number of spare general purpose registers (GPRx), which can be used as data registers, counters and so on. The file registers are numbered 00 to 4F, but are usually given labels in the program source code. File registers also give access to a block of EEPROM, which provides non-volatile data memory.
Clock and Reset
A clock circuit is connected to the timing and control block to drive all the operations of the chip. For applications where precise timing is not required, a simple external resistor and capacitor network controls the frequency of the internal oscillator. Relatively low frequencies are generated (< 1 MHz) with an RC clock. For more precise timing, a crystal oscillator is used (see data sheet Figure 6-7); a convenient frequency is 4 MHz, because each instruction takes four clock cycles to execute, that is, 1 ms. The exact program execution timing can then be more easily calculated, and the hardware timer used for accurate signal generation and measurement. With the high-speed oscillator option selected, the processor can be clocked at up to 20 MHz, giving a minimum 200 ns instruction execution period, and a maximum instruction execution rate of 5 mips (millions of instructions per second). Most current chips also include an internal oscillator that runs at frequencies between 32 kHz and 32 MHz; this is now the default option as it eliminates the external clock components.
In earlier processors, an external reset circuit was often needed to ensure a smooth start-up. Now, the timing and control circuits contain start-up timers, which means that the reset input !MCLR can simply be connected to VDD, the positive supply (normally via a precautionary resistor), to enable the processor. An external reset button (with a pull-up resistor) or control signal can still be connected to !MCLR if an external restart might be required. The MCU program can then be restarted by pulsing the reset input low. In most of our simple applications, the power-on reset will be used.
Harvard Architecture
It can be seen in the block diagrams that the memory and file register address lines are separate from the data paths within the processor. This is referred to as Harvard architecture; it improves the speed of processor operation because data and addresses do not have to share the same bus lines. The reduced size of the instruction set also speeds up decoding and the short data path length in a single chip design reduces data transmission time. The program execution hardware also uses a ‘pipeline’ arrangement; as one instruction is executed, the next is being fetched from program memory, overlapping instruction processing and thus doubling the overall execution rate. All these features contribute to a high speed of operation, compared with traditional microprocessors that use a conventional (Von Neumann) architecture, in which the program and data share the same data bus and memory space.