Simulation Test
The program can be tested in simulation mode before downloading to the LPC board. Assuming it has been edited and assembled in MPLAB, MPSIM can be invoked and the program run with the SFRs, stopwatch, etc., displayed. However, an analogue input stimulus is not available in MPSIM, so the ADRESH must be loaded via a register stimulus or a modified simulation version of the program used where a literal is loaded in place of the input. Otherwise, the program can only then be tested with the delay count loaded with 00 from ADRESH, giving the maximum delay.
Interactive simulation using Proteus VSM (Figure 7.4) is, therefore, in this case, simpler and more convenient. The program is written, assembled and attached to the MCU in the schematic, and the simulation run with source code and SFRs displayed (see Appendix E
for tutorial notes). The pot can be adjusted on screen and the LEDs will animate in real time, so correct program function can quickly be demonstrated. The program timing can be checked on the display of simulated time elapsed in the status bar.
The advantages of both systems can be realized by running the interactive simulation from within MPLAB. The debug tools provided by MPLAB are used to control the VSM simulation in a viewing window, while the interactive features are still available.
The simulation test allows the basic program syntax and logic to be checked before downloading. Any syntax errors will be detected by the assembler, with a line number indicated and the error type indicated in the output window. If the scanning output is not obtained, check the main sequence by single stepping through the main loop, stepping over the delay subroutine. If the sequence appears correct, view the SFRs and check that the changes are correct. If the main sequence and intialization are correct, step into the delay loop and make sure the program is not getting stuck in an endless loop and failing to return.