Register Operations
We will now briefly review some of the options available when using the file registers, which provide more flexibility in programming.
Result Destination
The default destination for single register operations can simply be specified by label or number. For example,
INCF spare
increments the register labeled ‘spare’, with the result being left in the register. The above syntax may generate a message when the program is assembled to remind the user that the ‘default’ destination is being used, unless messages are suppressed by specifying a list file option. The full syntax for the instruction is:
The label W is automatically given the value 0 by the assembler. The result of the operation is stored in W, while the original value is left unchanged in the file register. All the register arithmetic and logical byte operations have this option, except CLRF (Clear File Register) and CLRW (Clear Working Register), which are by definition register specific, and MOVWF and NOP (No OPeration). This option offers significant savings in execution time and program memory requirements, and also compensates to some extent for the absence of instructions that allow data to be transferred direct between file registers. These are available in higher power PICs that have a more extensive instruction set.
Register Bank Select
The smallest PICs, including the 16F84A, have a file register set (Figure 5.2) organized in two banks, with the most commonly used registers in the default bank 0. Some of the control registers, such as the port data direction registers, TRISA and TRISB, and the OPTION register, are mapped into bank 1. Many of the special function registers (SFRs) can be accessed in either bank. Others have used special access instructions, namely TRIS to write the port A and B data direction registers, and OPTION which is used to set up the hardware timer counter. The assembler warns that the instructions TRIS and OPTION may not be supported in future. However, at the time writing, they still work, and provide a simplified method of bank 1 access for the beginner.
Newer, more powerful PIC 16 chips can have up to 32 banks of RAM, so a more general method of bank selection is needed. Bank selection bits are provided in one of the SFRs, and these can be modified directly using BSF and BCF instructions. In the 16F84A, only one bit is needed, bit 5 in the status register, named RP0. Bank 0 is enabled by default (RP0 ¼ 0), thus bank 1 registers OPTION, TRISA, TRISB, EECON1 and EECON2 are accessed by setting RP0 ¼ 1, prior to operating on the required register. This explicit bank selection method is illustrated in the code fragment in the sequence below, which sets port B as output:
It is a good idea to reselect bank 0 immediately, as this is the most commonly used. If further bank 1 access is required, leave this step until later. Once a bank has been selected, it remains accessible until deselected. The larger PIC chips will need additional bank select bits.
An easier option is to use the pseudo-operation ‘BANKSEL’, which carries out the above process automatically:
BANKSEL selects the bank that the specified register is in, so any register in the required bank will do. BANKSEL is effectively a predefined ‘macro’, a sequence of instructions that are bundled together by the assembler and invoked using a user-defined label. Macros are explained more fully in Section 6.6, below.
File Register Indirect Addressing
Register 04 in the PIC 16 chip is the file select register (FSR). It is used for indirect or indexed addressing of the other file registers. A target file register address is loaded into FSR, and the contents of that file register can then be read or written at file register 00, the indirect file register (INDF). It is copied automatically to or from the target register. This method can be used for accessing a block of general purpose registers (GPRs), by reading or writing the data via INDF, and then selecting the next register in the data block by incrementing FSR. This indexed, indirect file register addressing is useful, for example, for storing a set of data that is read in at a port over a period of time. The technique is illustrated in Figure 6.7.
The demonstration program INX1 loads a set of file registers, 20 to 2F, with dummy data (AA), using FSR as the index register. FSR operates as a pointer to a block of locations, and is incremented between each read or write operation. Notice that the data actually has to be explicitly moved into INDF each time to trigger the file register write. The source code is seen in Program 6.3.
EEPROM Memory
PIC chips have a block of electrically erasable programmable read-only memory (EEPROM), which operates as non-volatile, read and write memory, where the data is retained when the power is off. This is useful, for example, in applications such as electronic lock, where the correct combination can be stored for comparison with an input code, but occasionally changed. Read from and write to EEPROM is illustrated in MPLAB in Figure 6.8. The code sequence can be seen in the source code window. Notice that the simulated input (09h) at port A is generated in a stimulus workbook window. The source code is listed as Program 6.4.
The set of registers used to access the EEPROM is EEDATA, EEADR, EECON1 and EECON2. The data to be stored is placed in EEDATA, and the address at which it is to be written in EEADR. Bank 1 must then be selected, and a read or write sequence included in the program as specified in the data sheet EEPROM section. The write sequence is designed to reduce the possibility of accidentally overwriting EEPROM, whereby essential data is lost. Reading the EEPROM is more straightforward, as seen in the second sequence in the source code.
Other devices use a different technique to access the EEPROM. For example, the 8-pin PIC 12CE518/9 devices use serial access via the unused bits of the port register. More recently introduced chips have extended the EEPROM write mechanism to include program memory read and write. The individual device data sheet must be studied carefully before using this feature.
Program Counter High Register, PCLATH
The basic 16 series PIC program memory can hold up to 8192 14-bit instructions (8k addresses). This requires a 13-bit address (213 ¼ 8192), so most of the chips in this group have a 13-bit program counter, even if the actual memory available is less than the maximum. Larger chips have a full 16-bit program counter, addressing up to 64k memory.
The 8-bit PCL (program counter low byte) can only select one of 256 addresses, so the program memory is effectively divided into pages of 256 instructions, in the same way that random access memory (RAM) is divided into banks of 256 locations. PCL provides the address within each page of memory and is fully readable and writable. The PCH (program counter high) register, which provides the high bytes of the program address, is not directly accessible, but can be manipulated via the PCLATH (program counter latch high byte) register. The way this works is different for programmed jumps and direct writes to PCL, as illustrated in Figure 6.9, with a 13-bit address. In either case, the data sheet must be studied carefully to avoid problems with jumps over page boundaries.
GOTO and CALL
When a programmed jump is requested, the low three bits of PCH are written with the high three bits from the 11-bit operand of the GOTO or CALL instruction. The PCLATH register provides the remaining two bits of the address. If the chip has 2k program memory or less, these bits have no effect. However, if the chip has more than 2k program memory (up to 8k, or 4 x 2k blocks), a GOTO or CALL across a 2k memory block boundary will need the PCLATH bits 3 and 4 to be modified explicitly. The CALL instruction must store all 13 bits of the return address on the stack before the high bits are replaced.
PCL Write
If PCL is modified by a direct write under program control, the upper five bits of the program counter will be loaded from PCLATH. If the jump crosses a page boundary, these bits must be corrected accordingly. This may be relevant if, for example, a data table crosses a page boundary (see Section 6.9 on data tables below). See Microchip’s ‘PIC Mid-Range MCU Family Reference Manual’ for further details. In other PIC chips, there may be other limitations to program branching operations. For example, CALL instructions in the 12C5XX
