Using ‘SPI’ peripherals:Hardware resource implications,Reliability and safety issues

Hardware resource implications

With on-chip hardware support, SPI PERIPHERAL imposes a minimal software load.

Reliability and safety issues

The SPI protocol incorporates only minimal error-checking mechanisms: detection of data corruption (for example) during the transfer of information to or from a periph- eral device must be carried out in software, if required.

Portability

This pattern requires hardware support for SPI: it cannot be used with microcontrollers without such support.

The discussions here are based on the Atmel 89S53. Use with other 8051 microcontrollers – including many Infineon 8051s – is straightforward.

Overall strengths and weaknesses

SPI is supported by a wide range of peripheral devices.

SPI requires (typically) three port pins for the bus, plus one chip-select pin per peripheral.

Use of hardware-based SPI (as discussed here) facilitates the design of tasks with short durations; as a consequence the protocol is well matched to the

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Related patterns and alternative solutions

The use of this pattern is restricted to microcontrollers with hardware support for SPI: see I 2 C PERIPHERAL [page 494] for an alternative solution that provides very similar facilities without the need for hardware support.

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