An introduction to shared-clock schedulers:Additional CPU performance and hardware facilities

In this chapter, we consider one additional important characteristic of embedded applications: the use of multiple processors. As we will see, the scheduler architecture introduced in previous chapters may be extended without difficulty in order to support such applications.

Introduction

Despite the diverse nature of the embedded applications we have discussed in previous chapters, each of these has involved only a single microcontroller. By contrast, many modern embedded systems contain more than one processor. For example, a modern passenger car might contain some 40 such devices (Leen et al., 1999), con- trolling brakes, door windows and mirrors, steering, air bags and so forth. Similarly, an industrial fire detection system might typically have 200 or more processors, asso- ciated, for example, with a range of different sensors and actuators.

We begin this chapter by considering two key advantages of multiprocessor sys- tems and then go on to introduce a form of co-operative scheduler – the shared-clock scheduler – that can help the developer get the most from such a design.

We conclude by discussing some of the reliability implications of multiprocessor implementations.

Additional CPU performance and hardware facilities

Suppose we require a microcontroller with the following specification:

● 60+ port pins

● Six timers

● Two USARTS

● 128 kbytes of ROM

● 512 bytes of RAM

● A cost of around $1.00 (US)

We can meet many of these requirements with an EXTENDED 8051 [page 46]: however, this will typically cost at the very least around 5–10 times the $1.00 price we require. By contrast, the ‘microcontroller’ in Figure 25.1 matches these requirements very closely.

Figure 25.1 shows two standard 8051 microcontrollers linked together by means of a single port pin: as we demonstrate in SCI SCHEDULER ( TICK ) [page 554], this type of scheduler can be created with a minimal software and hardware load. The result is a flexible environment with 62 free port pins, five free timers, two USARTs and so on. Note that further microcontrollers may be added without difficulty and the commu- nication over a single wire (plus ground) will ensure that the tasks on all processors are perfectly synchronized.

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Of course, in addition to the features listed, the two-microcontroller design also has two CPUs. In many (but not all) cases, this can allow you to perform tasks more quickly or to carry out more tasks within a given time interval.

The patterns LONG T ASK [page 716] and DOMINO T ASK [page 720], sometimes used in conjunction with DA T A UNION [Page 712], encapsulate effective software architec- tures that allow you to get the best performance out of such a multiprocessor design.

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