THE 8237 DMA CONTROLLER
The 8237 DMA controller supplies the memory and I/O with control signals and memory address information during the DMA transfer. The 8237 is actually a special-purpose micro- processor whose job is high-speed data transfer between memory and the I/O. Figure 13–3 shows the pin-out and block diagram of the 8237 programmable DMA controller. Although this device may not appear as a discrete component in modern microprocessor-based systems, it does appear within system controller chip sets found in most systems. Although not described because of its complexity, the modern chip set (ISP or integrated system peripheral controller) and its integral set of two DMA controllers are programmed almost exactly (it does not support memory-to-memory transfers) like the 8237. The ISP also provides a pair of 8259A programmable interrupt controllers for the system.
The 8237 is a four-channel device that is compatible with the 8086/8088 microprocessors. The 8237 can be expanded to include any number of DMA channel inputs, although four channels seem to be adequate for many small systems. The 8237 is capable of DMA transfers at rates of up to 1.6M bytes per second. Each channel is capable of addressing a full 64K-byte section of memory and can transfer up to 64K bytes with a single programming.
Pin Definitions
CLK The clock input is connected to the system clock signal as long as that signal is 5 MHz or less. In the 8086/8088 system, the clock must be inverted for the proper operation of the 8237.
CS Chip select enables the 8237 for programming. The CS pin is normally connected to the output of a decoder. The decoder does not use the 8086/8088 control signal IO>M(M>IO) because it contains the new memory and I/O control signals (MEMR, MEMW, IOR, and IOW).
RESET The reset pin clears the command, status, request, and temporary registers. It also clears the first/last flip-flop and sets the mask register. This input primes the 8237 so it is disabled until programmed otherwise.
READY A logic 0 on the ready input causes the 8237 to enter wait states for slower memory components.
HLDA A hold acknowledge signals the 8237 that the microprocessor has relinquished control of the address, data, and control buses.
DREQ0–DREQ3 The DMA request inputs are used to request a DMA transfer for each of the four DMA channels. Because the polarity of these inputs is programmable, they are either active-high or active-low inputs.
DB0–DB7 The data bus pins are connected to the microprocessor data bus connections and are used during the programming of the DMA controller.
IOR IOW EOP
I/O read is a bidirectional pin used during programming and during a DMA write cycle.
I/O write is a bidirectional pin used during programming and during a DMA read cycle.
End-of-process is a bidirectional signal that is used as an input to terminate a DMA process or as an output to signal the end of the DMA transfer. This input is often used to interrupt a DMA transfer at the end of a DMA cycle.
A0–A3 These address pins select an internal register during programming and also provide part of the DMA transfer address during a DMA action.
The address pins are outputs that provide part of the DMA transfer address during a DMA action.
HRQ Hold request is an output that connects to the HOLD input of the microprocessor in order to request a DMA transfer.
DACK0–DACK3 DMA channel acknowledge outputs acknowledge a channel DMA request. These outputs are programmable as either active-high or active low signals. The DACK outputs are often used to select the DMA- controlled I/O device during the DMA transfer.
AEN The address enable signal enables the DMA address latch connected to the DB7–DB0 pins on the 8237. It is also used to disable any buffers in the system connected to the microprocessor.
ADSTB Address strobe functions as ALE, except that it is used by the DMA controller to latch address bits A15–A8 during the DMA transfer.
MEMR MEMW
Memory read is an output that causes memory to read data during a DMA read cycle.
Memory write is an output that causes memory to write data during a DMA write cycle.
Internal Registers
CAR The current address register is used to hold the 16-bit memory address used for the DMA transfer. Each channel has its own current address register for this purpose. When a byte of data is transferred during a DMA operation, the CAR is either incremented or decremented, depending on how it is programmed.
CWCR The current word count register programs a channel for the number of bytes (up to 64K) transferred during a DMA action. The number loaded into this register is one less than the number of bytes transferred. For example, if a 10 is loaded into the CWCR, then 11 bytes are transferred during the DMA action.
BA and BWC The base address (BA) and base word count (BWC) registers are used when auto-initialization is selected for a channel. In the auto-initialization mode, these registers are used to reload both the CAR and CWCR after the DMA action is completed. This allows the same count and address to be used to transfer data from the same memory area.
CR The command register programs the operation of the 8237 DMA controller. Figure 13–4 depicts the function of the command register. The command register uses bit position 0 to select the memory-to-memory DMA transfer mode. Memory-to-memory DMA transfers use DMA
channel 0 to hold the source address and DMA channel 1 to hold the destination address. (This is similar to the operation of a MOVSB instruction.) A byte is read from the address accessed by channel 0 and saved within the 8237 in a temporary holding register. Next, the 8237 initiates a memory write cycle in which the contents of the temporary holding register are written into the address selected by DMA channel
1. The number of bytes transferred is determined by the channel 1 count register.
The channel 0 address hold enable bit (bit position 1) programs channel 0 for memory-to-memory transfers. For example, if you must fill an area of memory with data, channel 0 can be held at the same address while channel 1 changes for memory-to-memory transfer. This copies the contents of the address accessed by channel 0 into a block of memory accessed by channel 1.
The controller enable/disable bit (bit position 2) turns the entire controller on and off. The normal and compressed bit (bit position 3) determine whether a DMA cycle contains two (compressed) or four (normal) clocking periods. Bit position 5 is used in normal timing to extend the write pulse so it appears one clock earlier in the timing for I/O devices that require a wider write pulse.
Bit position 4 selects priority for the four DMA channel DREQ inputs. In the fixed priority scheme, channel 0 has the highest priority and channel 3 has the lowest. In the rotating priority scheme, the most recently serviced channel assumes the lowest priority. For example,
if channel 2 just had access to a DMA transfer, it assumes the lowest priority and channel 3 assumes the highest priority position. Rotating priority is an attempt to give all channels equal priority.
The remaining two bits (bit positions 6 and 7) program the polarities of the DREQ inputs and the DACK outputs.
MR The mode register programs the mode of operation for a channel. Note that each channel has its own mode register (see Figure 13–5), as selected by bit positions 1 and 0. The remaining bits of the mode register select the operation, auto-initialization, increment/decrement, and
mode for the channel. Verification operations generate the DMA addresses without generating the DMA memory and I/O control signals.
The modes of operation include demand mode, single mode, block mode, and cascade mode. Demand mode transfers data until an external EOP is input or until the DREQ input becomes inactive. Single mode releases the HOLD after each byte of data is transferred. If the DREQ pin is held active, the 8237 again requests a DMA transfer through the DRQ line to the microprocessor’s HOLD input. Block mode automatically transfers the number of bytes indicated by the count register for the channel. DREQ need not be held active through the block mode transfer. Cascade mode is used when more than one 8237 is present in a system.
BR The bus request register is used to request a DMA transfer via soft- ware (see Figure 13–6). This is very useful in memory-to-memory transfers, where an external signal is not available to begin the DMA transfer.
MRSR The mask register set/reset sets or clears the channel mask, as illustrated in Figure 13–7. If the mask is set, the channel is disabled. Recall that the RESET signal sets all channel masks to disable them.
MSR The mask register (see Figure 13–8) clears or sets all of the masks with one command instead of individual channels, as with the MRSR.
SR The status register shows the status of each DMA channel (see Figure 13–9). The TC bits indicate whether the channel has reached its terminal count (transferred all its bytes). Whenever the terminal count is reached, the DMA transfer is terminated for most modes of operation.
The request bits indicate whether the DREQ input for a given channel is active.
Software Commands
Three software commands are used to control the operation of the 8237. These commands do not have a binary bit pattern, as do the various control registers within the 8237. A simple output to the correct port number enables the software command. Figure 13–10 shows the I/O port assignments that access all registers and the software commands.
The functions of the software commands are explained in the following list:
1. Clear the first/last flip-flop—Clears the first/last (F/L) flip-flop within the 8237. The F/L flip-flop selects which byte (low or high order) is read/written in the current address and cur- rent count registers. If F/L = 0, the low-order byte is selected; if F/L = 1, the high-order byte is selected. Any read or write to the address or count register automatically toggles the F/L flip-flop.
2. Master clear—Acts exactly the same as the RESET signal to the 8237. As with the RESET signal, this command disables all channels.
3. Clear mask register—Enables all four DMA channels.
Programming the Address and Count Registers
Figure 13–11 illustrates the I/O port locations for programming the count and address registers for each channel. Notice that the state of the F/L flip-flop determines whether the LSB or MSB is programmed. If the state of the F/L flip-flop is unknown, the count and address could be programmed incorrectly. It is also important that the DMA channel be disabled before its address and count are programmed.
Four steps are required to program the 8237: (1) The F/L flip-flop is cleared using a clear F/L command; (2) the channel is disabled; (3) the LSB and then MSB of the address are programmed; and (4) the LSB and MSB of the count are programmed. Once these four operations are performed, the channel is programmed and ready to use. Additional programming is required to select the mode of operation before the channel is enabled and started.
The 8237 Connected to the 80X86 Microprocessor
Figure 13–12 shows an 80X86-based system that contains the 8237 DMA controller.
The address enable (AEN) output of the 8237 controls the output pins of the latches and the outputs of the 74LS257 (E). During normal 80X86 operation (AEN = 0), latches A and C and the multiplexer (E) provide address bus bits A19–A16 and A7–A0. The multiplexer provides the
system control signals as long as the 80X86 is in control of the system. During a DMA action (AEN = 1), latches A and C are disabled along with the multiplexer (E). Latches D and B now provide address bits A19–A16 and A15–A8. Address bus bits A7–A0 are provided directly by the 8237 and contain a part of the DMA transfer address. The control signals MEMR, MEMW, IOR, and IOW are provided by the DMA controller.
The address strobe output (ADSTB) of the 8237 clocks the address (A15–A8) into latch D during the DMA action so that the entire DMA transfer address becomes available on the address bus. Address bus bits A19–A16 are provided by latch B, which must be programmed with these four address bits before the controller is enabled for the DMA transfer. The DMA operation of the 8237 is limited to a transfer of not more than 64K bytes within the same 64K-byte section of the memory.
The decoder (F) selects the 8237 for programming and the 4-bit latch (B) for the upper- most four address bits. The latch in a PC is called the DMA page register (8 bits) that holds address bits A16–A23 for a DMA transfer. A high page register also exists, but its address is chip- dependent. The port numbers for the DMA page registers are listed in Table 13–1 (these are for the Intel ISP). The decoder in this system enables the 8237 for I/O port addresses XX60H–XX7FH, and the I/O latch (B) for ports XX00H–XX1FH. Notice that the decoder out- put is combined with the IOW signal to generate an active-high clock for the latch (B).
During normal 80X86 operation, the DMA controller and integrated circuits B and D are disabled. During a DMA action, integrated circuits A, C, and E are disabled so that the 8237 can take control of the system through the address, data, and control buses.
In the personal computer, the two DMA controllers are programmed at I/O ports 0000H–000FH for DMA channels 0–3, and at ports 00C0H–00DFH for DMA channels 4–7. Note that the second controller is programmed at even addresses only, so the channel 4 base and current address is programmed at I/O port 00C0H and the channel 4 base and current count is programmed at port 00C2H. The page register, which holds address bits A23–A16 of the DMA
address, is located at I/O ports 0087H (CH-0), 0083H (CH-1), 0081H (CH-2), 0082H (CH-3),
(no channel 4), 008BH (CH-5), 0089H (CH-6), and 008AH (CH-7). The page register functions as the address latch described with the examples in this text.
Memory-to-Memory Transfer with the 8237
The memory-to-memory transfer is much more powerful than even the automatically repeated MOVSB instruction. (Note: Most modern chip sets do not support the memory-to-memory feature.) Although the repeated MOVSB instruction tables show that the 8088 requires 4.2 μs per byte, the 8237 requires only 2.0 μs per byte, which is over twice as fast as a software data transfer. This is not true if an 80386, 80846, or Pentium through Pentium 4 is in use in the system.
Sample Memory-to-Memory DMA Transfer. Suppose that the contents of memory locations 10000H–13FFFH are to be transferred into memory locations 14000H–17FFFH. This is accomplished with a repeated string move instruction or, at a much faster rate, with the DMA controller.
Programming the DMA controller requires a few steps, as illustrated in Example 13–1. The leftmost digit of the 5-digit address is sent to latch B. Next, the channels are programmed after the F/L flip-flop is cleared. Note that we use channel 0 as the source and channel 1 as the destination for a memory-to-memory transfer. The count is next programmed with a value that is one less than the number of bytes to be transferred. Next, the mode register of each channel is programmed, the command register selects a block move, channel 0 is enabled, and a software DMA request is initiated. Before return is made from the procedure, the status register is tested for a terminal count. Recall that the terminal count flag indicates that the DMA transfer is completed. The TC also disables the channel, preventing additional transfers.
Sample Memory Fill Using the 8237. In order to fill an area of memory with the same data, the channel 0 source register is programmed to point to the same address throughout the transfer. This is accomplished with the channel 0 hold mode. The controller copies the contents of this single memory location to an entire block of memory addressed by channel 1. This has many useful applications.
For example, suppose that a DOS video display must be cleared. This operation can be per- formed using the DMA controller with the channel 0 hold mode and a memory-to-memory trans- fer. If the video display contains 80 columns and 25 lines, it has 2000 display positions that must be set to 20H (an ASCII space) to clear the screen.
Example 13–2 shows a procedure that clears an area of memory addressed by ES:DI. The CX register transfers the number of bytes to be cleared to the CLEAR procedure. Notice that this procedure is nearly identical to Example 13–1, except that the command register is programmed so the channel 0 address is held. The source address is programmed as the same address as ES:DI, and then the destination is programmed as one location beyond ES:DI. Also note that this program is designed to function with the hardware in Figure 13–12 and will not function in the personal computer unless you have the same hardware.
DMA-Processed Printer Interface
Figure 13–13 illustrates the hardware added to Figure 13–12 for a DMA-controlled printer inter- face. Little additional circuitry is added for this interface to a Centronics-type parallel printer. The latch is used to capture the data as it is sent to the printer during the DMA transfer. The write pulse passed through to the latch during the DMA action also generates the data strobe (DS) signal to the printer through the single-shot. The ACK signal returns from the printer each time it is ready for additional data. In this circuit, ACK is used to request a DMA action through a flip-flop.
Notice that the I/O device is not selected by decoding the address on the address bus. During the DMA transfer, the address bus contains the memory address and cannot contain the I/O port address. In place of the I/O port address, the DACK3 output from the 8237 selects the latch by gating the write pulse through an OR gate.
Software that controls this interface is simple because only the address of the data and the number of characters to be printed are programmed. Once programmed, the channel is
enabled, and the DMA action transfers a byte at a time to the printer interface each time that the interface receives the ACK signal from the printer.
The procedure that prints data from the current data segment is illustrated in Example 13–3. This procedure programs the 8237, but doesn’t actually print anything. Printing is accomplished by the DMA controller and the printer interface.
A secondary procedure is needed to determine whether the DMA action has been completed. Example 13–4 lists the secondary procedure that tests the DMA controller to see whether the DMA transfer is complete. The TESTP procedure is called before programming the DMA controller to see whether the prior transfer is complete.
Printed data can be double-buffered by first loading buffer 1 with data to be printed. Next, the PRINT procedure is called to begin printing buffer 1. Because it takes very little time to pro- gram the DMA controller, a second buffer (buffer 2) can be filled with new printer data while the first buffer (buffer 1) is printed by the printer interface and DMA controller. This process is repeated until all data are printed.