SUMMARY
1. All memory devices have address inputs; data inputs and outputs, or just outputs; a pin for selection; and one or more pins that control the operation of the memory.
2. Address connections on a memory component are used to select one of the memory locations within the device. Ten address pins have 1024 combinations and therefore are able to address 1024 different memory locations.
3. Data connections on a memory are used to enter information to be stored in a memory location and also to retrieve information read from a memory location. Manufacturers list their
7. The flash memory (EEPROM) is programmed in the system by using a 12 V or 5.0 V programming pulse.
8. Static RAM (SRAM) retains data for as long as the system power supply is attached. These memory types are available in sizes up to 128K × 8.
9. Dynamic RAM (DRAM) retains data for only a short period, usually 2–4 ms. This creates problems for the memory system designer because the DRAM must be refreshed periodically. DRAMs also have multiplexed address inputs that require an external multiplexer to provide each half of the address at the appropriate time.
10. Memory address decoders select an EPROM or RAM at a particular area of the memory.
Commonly found address decoders include the 74LS138 3-to-8 line decoder, the 74LS139 2-to-4 line decoder, and programmed selection logic in the form of a PLD.
11. The PLD address decoder for microprocessors like the 8088 through the Pentium 4 reduce the number of integrated circuits required to complete a functioning memory system.
12. The 8088 minimum mode memory interface contains 20 address lines, eight data lines, and three control lines: RD, WR, and IO>M. The 8088 memory functions correctly only when all these lines are used for memory interface.
13. The access speed of the EPROM must be compatible with the microprocessor to which it is interfaced. Many EPROMs available today have an access time of 450 ns, which is too slow for the 5 MHz 8088. In order to circumvent this problem, a wait state is inserted to increase memory access time to 660 ns.
14. Error-correction features are also available for memory systems, but these require the storage of many more bits. If an 8-bit number is stored with an error-correction circuit, it actually takes 13 bits of memory: five for an error checking code and eight for the data. Most error-correction integrated circuits are able to correct only a single-bit error.
15. The 8086/80286/80386SX memory interface has a 16-bit data bus and contains an M>IO control pin, whereas the 8088 has an 8-bit data bus and contains an IO>M pin. In addition to these changes, there is an extra control signal, bus high enable (BHE).
16. The 8086/80386/80386SX memory is organized in two 8-bit banks: high bank and low bank. The high bank of memory is enabled by the BHE control signal and the low bank is enabled by the A0 address signal or by the BLE control signal.
17. Two common schemes for selecting the banks in an 8086/80286/80386SX-based system include (1) a separate decoder for each bank and (2) separate WR control signals for each bank with a common decoder.
18. Memory interfaced to the 80386DX and 80486 is 32 bits wide, as selected by a 32-bit address bus. Because of the width of this memory, it is organized in four memory banks that are each 8 bits wide. Bank selection signals are provided by the microprocessor as BE3, BE2, BE1, and BE0.
19. Memory interfaced to the Pentium–Core2 is 64 bits wide, as selected by a 32-bit address bus. Because of the width of the memory, it is organized in eight banks that are each 8 bits wide. Bank selection signals are provided by the microprocessor as BE7–BE0.
20. Dynamic RAM controllers are designed to control DRAM memory components. Many DRAM controllers today are built into the chip set and contain address multiplexers, refresh counters, and the circuitry required to do a periodic DRAM memory refresh.