QUESTIONS AND PROBLEMS
1. What types of connections are common to all memory devices?
2. List the number of words found in each memory device for the following numbers of address connections:
(a) 8
(b) 11
(c) 12
(d) 13
(e) 20
3. List the number of data items stored in each of the following memory devices and the number of bits in each datum:
(a) 2K × 4
(b) 1K × l
(c) 4K × 8
(d) 16K × 1
(e) 64K × 4
4. What is the purpose of the CS or CE pin on a memory component?
5. What is the purpose of the OE pin on a memory device?
6. What is the purpose of the WE pin on a SRAM?
7. How many bytes of storage do the following EPROM memory devices contain? (a) 2708
(b) 2716
(c) 2732
(d) 2764
(e) 27512
8. Why won’t a 450 ns EPROM work directly with a 5 MHz 8088?
9. What can be stated about the amount of time needed to erase and write a location in a flash memory device?
10. SRAM is an acronym for what type of device?
11. The 4016 memory has a G pin, an S pin, and a W pin. What are these pins used for in this RAM?
12. How much memory access time is required by the slowest 4016?
13. DRAM is an acronym for what type of device?
14. The 256M DIMM has 28 address inputs, yet it is a 256M DRAM. Explain how a 28-bit memory address is forced into 14 address inputs.
15. What are the purposes of the CAS and RAS inputs of a DRAM?
16. How much time is required to refresh the typical DRAM?
17. Why are memory address decoders important?
18. Modify the NAND gate decoder of Figure 10–13 to select the memory for address range DF800H–DFFFFH.
19. Modify the NAND gate decoder in Figure 10–13 to select the memory for address range 40000H–407FFH.
20. When the G1 input is high and both G2A and G2B are low, what happens to the outputs of the 74HCT138 3-to-8 line decoder?
21. Modify the circuit of Figure 10–15 to address memory range 70000H–7FFFFH.
22. Modify the circuit of Figure 10–15 to address memory range 40000H–4FFFFH.
23. Describe the 74LS139 decoder.
24. What is VHDL?
25. What are the five major keywords in VHDL for the five major logic functions (AND, OR, NAND, NOR, and invert)?
26. Equations are placed in what major block of a VHDL program?
27. Modify the circuit of Figure 10–19 by rewriting the PLD program to address memory at locations A0000H–BFFFFH for the ROM.
28. The RD and WR minimum mode control signals are replaced by what two control signals in the 8086 maximum mode?
29. Modify the circuit of Figure 10–20 to select memory at location 60000H–77FFFH.
30. Modify the circuit of Figure 10–20 to select eight 27256 32K × 8 EPROMs at memory locations 40000H–7FFFFH.
31. Add another decoder to the circuit of Figure 10–21 so that an additional eight 62256 SRAMs are added at locations C0000H–FFFFFH.
32. The 74LS636 error-correction and detection circuit stores a check code with each byte of data. How many bits are stored for the check code?
33. What is the purpose of the SEF pin on the 74LS636?
34. The 74LS636 will correct bits that are in error.
35. Outline the major difference between the buses of the 8086 and 8088 microprocessors.
36. What is the purpose of the BHE and A0 pins on the 8086 microprocessor?
37. What is the BLE pin and what other pin has it replaced?
38. What two methods are used to select the memory in the 8086 microprocessor?
39. If BHE is a logic 0, then the memory bank is selected.
40. If A0 is a logic 0, then the memory bank is selected.
41. Why don’t separate bank read (RD) strobes need to be developed when interfacing memory
to the 8086?
42. Modify the circuit of Figure 10–30 so that the RAM is located at memory range 30000H–4FFFFH.
43. Develop a 16-bit-wide memory interface that contains SRAM memory at locations 200000H–21FFFFH for the 80386SX microprocessor.
44. Develop a 32-bit-wide memory interface that contains EPROM memory at locations FFFF0000H–FFFFFFFFH.
45. Develop a 64-bit-wide memory for the Pentium–Core2 that contains EPROM at locations FFF00000H–FFFFFFFFH and SRAM at locations 00000000H–003FFFFFH.
46. On the Internet, search for the largest size EEPROM you can find. List its size and manufacturer.
47. What is an RAS-only cycle?
48. Can a DRAM refresh be done while other sections of the memory operate?
49. If a 1M × 1 DRAM requires 4 ms for a refresh and has 256 rows to be refreshed, no more than of time must pass before another row is refreshed.
50. How wide is the data bus in the Intel Itanium?
51. Scour the Internet to find the largest DRAM currently available.
52. Write a report on DDR memory. (Hint: Samsung makes them.)
53. Write a report that details RAMBUS RAM. Try to determine why this technology appears to have fallen by the wayside.